US2002100959A1PendingUtilityA1

Capacitor for semiconductor memory device and method of manufacturing the same

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Assignee: HYUNDAI ELECTRONICS INDPriority: Jul 2, 1999Filed: Mar 4, 2002Published: Aug 1, 2002
Est. expiryJul 2, 2019(expired)· nominal 20-yr term from priority
Inventors:Kwang Chul JooKee-Jeung LeeIl Keoun Han
H10P 14/69433H10P 14/69393H10P 14/6544H10P 14/6538H10P 14/6532H10P 14/6334H10P 14/6316H10D 1/712H10D 1/684H10D 1/692H10D 1/68H10B 12/033
39
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Claims

Abstract

Disclosed are a capacitor for a semiconductor memory device and a method of manufacturing the same. According to the present invention, the method includes the steps of: forming a lower electrode on a semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta 2 O 5 layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta 2 O 5 layer; and forming an upper electrode on the upper part of the conductive barrier.

Claims

exact text as granted — not AI-modified
What is claim is:  
     
         1 . A capacitor for a semiconductor memory device comprising: 
 a lower electrode;    a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface;    a dielectric layer formed on the upper part of the silicon nitride layer; and    an upper electrode formed on the upper part of the dielectric layer,    wherein the dielectric layer is a Ta 2 O 5  layer.    
     
     
         2 . The capacitor according to  claim 1 , comprising a conductive barrier made of the silicon nitride layer between the dielectric layer and the upper electrode.  
     
     
         3 . The capacitor according to  claim 2 , wherein the thickness of the conductive barrier is 10 to 20Å.  
     
     
         4 . The capacitor according to  claim 1 , wherein the lower electrode has cylinder or stack structure which an HSG layer is formed on the surface thereof.  
     
     
         5 . The capacitor according to  claim 1 , wherein the thickness of the Ta 2 O 5  layer is 100 to 150Å.  
     
     
         6 . The capacitor according to  claim 1 , wherein the upper electrode is formed of a doped polysilicon layer.  
     
     
         7 . The capacitor according to  claim 1 , wherein the upper electrode is formed of a metal layer.  
     
     
         8 . The capacitor according to  claim 6 , wherein the metal layer is one among TiN, TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2  and Pt.  
     
     
         9 . A capacitor for a semiconductor memory device comprising: 
 a lower electrode;    a silicon nitride layer for restraint of a natural oxide layer formed on the lower electrode surface;    a dielectric layer formed on the upper part of the silicon nitride layer;    a conductive barrier made of the silicon nitride layer formed on the dielectric layer surface; and    an upper electrode formed on the upper part of the conductive barrier,    wherein the dielectric layer is a Ta 2 O 5  layer.    
     
     
         10 . The capacitor according to  claim 9 , wherein the thickness of the conductive barrier is 10 to 20Å.  
     
     
         11 . The capacitor according to  claim 9 , wherein the lower electrode is cylinder or stack structure which an HSG layer is formed on the surface thereof.  
     
     
         12 . The capacitor according to  claim 9 , wherein the thickness of the Ta 2 O 5  layer is 100 to 150Å.  
     
     
         13 . The capacitor according to  claim 9 , wherein the upper electrode is formed of a doped polysilicon layer.  
     
     
         14 . The capacitor according to  claim 9 , wherein the upper electrode is formed of a metal layer.  
     
     
         15 . The capacitor according to  claim 14 , wherein the metal layer is one among TiN, TaN, W, WN, Wsi, Ru, RuO 2 , Ir, IrO 2 , and Pt.

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