US2002121695A1PendingUtilityA1

Molded ball grid array

40
Priority: May 11, 2000Filed: Apr 11, 2002Published: Sep 5, 2002
Est. expiryMay 11, 2020(expired)· nominal 20-yr term from priority
H10W 90/756H10W 90/754H10W 90/734H10W 72/865H10W 74/016H10W 74/111
40
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A molded ball grid array comprising: 
 a substrate comprising a first surface and a second surface, the second surface having a plurality of pads thereon;    a semiconductor chip coupled to the first surface of the substrate; and    molding compound deposited on the first surface and on the second surface of the substrate, the molding compound deposited on the second surface of the substrate forming a plurality of cups arranged to expose at least a portion of each of the plurality of pads on the second surface of the substrate.    
     
     
         2 . The molded ball grid array, as set forth in  claim 1 , wherein the plurality of pads are comprised of a conductive material.  
     
     
         3 . The molded ball grid array, as set forth in  claim 1 , wherein the semiconductor chip comprises a memory device.  
     
     
         4 . The molded ball grid array, as set forth in  claim 1 , wherein the semiconductor chip is electrically coupled to the substrate.  
     
     
         5 . The molded ball grid array, as set forth in  claim 1 , wherein the molding compound is disposed on at least a portion of the semiconductor chip.  
     
     
         6 . The molded ball grid array, as set forth in  claim 1 , wherein the molding compound comprises a resin.  
     
     
         7 . The molded ball grid array, as set forth in  claim 1 , wherein the plurality of pads are fully exposed within the respective plurality of cups.  
     
     
         8 . The molded ball grid array, as set forth in  claim 1 , wherein each of the plurality of cups is configured to receive a solder ball.  
     
     
         9 . The molded ball grid array, as set forth in  claim 1 , wherein the plurality of cups are tapered in shape.  
     
     
         10 . The molded ball grid array, as set forth in  claim 1 , wherein the plurality of cups are hemispherical in shape.  
     
     
         11 . The molded ball grid array, as set forth in  claim 1 , wherein the plurality of cups are cylindrical in shape.  
     
     
         12 . A system comprising: 
 a processor; and    a memory circuit operatively coupled to the processor, the memory circuit comprising: 
 a substrate comprising a first surface and a second surface, the second surface having a plurality of pads thereon;  
 a semiconductor chip coupled to the first surface of the substrate; and  
 molding compound deposited on the first surface and on the second surface of the substrate, the molding compound deposited on the second side of the substrate, forming a plurality of cups arranged to expose at least a portion of each of the plurality of pads on the second surface of the substrate.  
   
     
     
         13 . The system, as set forth in  claim 12 , wherein the plurality of pads are comprised of a conductive material.  
     
     
         14 . The system, as set forth in  claim 12 , wherein the semiconductor chip is a memory device.  
     
     
         15 . The system, as set forth in  claim 12 , wherein the semiconductor chip is electrically coupled to the substrate.  
     
     
         16 . The system, as set forth in  claim 12 , wherein the molding compound is disposed on at least a portion of the semiconductor chip.  
     
     
         17 . The system, as set forth in  claim 12 , wherein the molding compound is a resin.  
     
     
         18 . The system, as set forth in  claim 12 , wherein the plurality of pads are fully exposed within the respective plurality of cups.  
     
     
         19 . The system, as set forth in  claim 12 , wherein each of the plurality of cups is configured to receive a solder ball.  
     
     
         20 . The system, as set forth in  claim 12 , wherein the plurality of cups are tapered in shape.  
     
     
         21 . The system, as set forth in  claim 12 , wherein the plurality of cups are hemispherical in shape.  
     
     
         22 . The system, as set forth in  claim 12 , wherein the plurality of cups are cylindrical in shape.  
     
     
         23 . A memory module comprising: 
 a substrate comprising a first surface and a second surface, the second surface having a plurality of pads thereon;    a plurality of memory chips coupled to the first surface of the substrate; and    molding compound deposited on the first surface and on the second surface of the substrate, the molding compound deposited on the second side of the substrate, forming a plurality of cups arranged to expose at least a portion of each of the plurality of pads on the second surface of the substrate.    
     
     
         24 . A system for molding a substrate in a circuit package comprising: 
 a first support plate; and    a second support plate proximately positioned with respect to the first support plate, the second support plate comprising protrusions configured to form cups in the package to align with pads on the substrate.    
     
     
         25 . The system, as set forth in  claim 24 , wherein the protrusions are tapered.  
     
     
         26 . A method of molding a circuit package comprising the acts of: 
 (a) disposing a first mold adjacent a circuit package comprising a semiconductor device coupled to a substrate;    (b) disposing a second mold adjacent the circuit package such that protrusions extending from the second mold are brought in contact with pads on the substrate; and    (c) injecting a molding compound between the first and second molds and over at least a portion of the circuit package.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.