Process and structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits

Abstract

A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

What is claimed is:  
     
         1 . An integrated capacitor comprising: 
 a bottom electrode layer,    a dielectric layer disposed on the bottom electrode layer,    a top electrode layer disposed on the dielectric layer; and    a conductive hardmask layer disposed on the top electrode layer.    
     
     
         2 . The integrated capacitor of  claim 1 , wherein the dielectric layer comprises a ferroelectric dielectric material.  
     
     
         3 . The integrated capacitor of  claim 2 , wherein the conductive hardmask layer comprises strontium ruthenium oxide.  
     
     
         4 . The integrated capacitor of  claim 3 , wherein the top electrode layer comprises a noble metal oxide.  
     
     
         5 . The integrated capacitor of  claim 4 , wherein the bottom electrode layer comprises a noble metal.  
     
     
         6  The integrated capacitor of  claim 5 , wherein the bottom electrode layer comprises platinum, the dielectric layer comprises lead-zirconium-titanate, and the top electrode layer comprises iridium oxide.  
     
     
         7 . The integrated capacitor of  claim 6 , further comprising an adhesion layer and a passivation layer.