Manufacturing method of semiconductor device

Abstract

A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H 2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an insulation layer including a low dielectric film having a bond of Si and a group made of organic constituents;    a wiring material embedded, through a barrier metal, in one of a via hole and a wiring groove formed in said insulation layer; and    a layer formed between said low dielectric film and said barrier metal and has a relatively low concentration of organic constituents in comparison with said low dielectric film.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein a concentration of carbon (C) of said layer having the relatively low concentration of organic constituents in comparison with said low dielectric interlayer film is 7 atom % or below.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein a concentration of carbon (C) of said layer having the relatively low concentration of organic constituents in comparison with said low dielectric interlayer film is 7 atom % or below and 2 atom % or above.  
     
     
         4 . The semiconductor device according to  claim 1 , wherein said layer having a relatively low concentration of organic constituents in comparison with said low dielectric interlayer film has a film thickness of 25 nm or less.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein said layer having a relatively low concentration of organic constituents in comparison with said low dielectric interlayer film has a bond of Si and hydrogen (H).  
     
     
         6 . The semiconductor device according to  claim 1 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.  
     
     
         7 . The semiconductor device according to  claim 1 , wherein said barrier metal is made of tantalum nitride (TaN) on a side of said low dielectric film and tantalum (Ta) on a side of said wiring material.  
     
     
         8 . A manufacturing method of a semiconductor device comprising the steps of: 
 conducting a plasma treatment using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of a low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond; and then    embedding, through a barrier metal, a wiring material in one of a via hole and a wiring groove formed in an insulation layer including said low dielectric film having a bond of Si and a group made of organic constituents.    
     
     
         9 . A manufacturing method of a semiconductor device, comprising the steps of: 
 forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed;    forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a first resist pattern formed on said second interlayer insulation film;    removing said first resist pattern and then. forming a trench pattern through etching of said second interlayer insulation film using a second resist pattern formed on said second interlayer insulation film;    depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern;    depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and    removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein: 
 at least one of said first interlayer insulation film and said second interlayer insulation film is a low dielectric film having a bond of Si and a group made of organic constituents; and  
 a plasma treatment is performed before said barrier metal is deposited, using one of a gas capable of replacing at least part of the group made of organic constituents on an exposed surface of said low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.  
   
     
     
         10 . A manufacturing method of a semiconductor device, comprising the steps of: 
 depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed;    forming a hard mask through etching of said hard mask material using a first resist pattern formed on said hard mask material;    forming a via hole penetrating through said first interlayer insulation film and said second-interlayer insulation film using a second resist pattern formed on said hard mask;    removing said second resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using said hard mask;    depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern; and    depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and    removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein: 
 at least one of said first interlayer insulation film, said second interlayer insulation film, and said hard mask is a low dielectric film having a bond of Si and a group made of organic constituents; and  
 a plasma treatment is performed before said barrier metal is deposited, using one of a gas. capable of replacing at least part of the group made of organic constituents on an exposed surface of said low dielectric film with hydrogen, and a gas capable of decomposing at least part of the group made of organic constituents to form a dangling bond.  
   
     
     
         11 . The manufacturing method of a semiconductor device according to  claim 8 , wherein said plasma treatment and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.  
     
     
         12 . The manufacturing method of a semiconductor device according to  claim 9 , wherein said plasma treatment and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.  
     
     
         13 . The manufacturing method of a semiconductor device according to  claim 10 , wherein said plasma treatment and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.  
     
     
         14 . The manufacturing method of a semiconductor device according to  claim 8 , further comprising the step of performing sputtering using an Ar gas prior to said plasma treatment, wherein said Ar sputtering, said plasma treatment, and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.  
     
     
         15 . The manufacturing method of a semiconductor device according to  claim 9 , further comprising the step of performing sputtering using an Ar gas prior to said plasma treatment, wherein said Ar sputtering, said plasma treatment, and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.  
     
     
         16 . The manufacturing method of a semiconductor device according to  claim 10 , further comprising the step of performing sputtering using an Ar gas prior to said plasma treatment, wherein said Ar sputtering, said plasma treatment, and said depositing of said barrier metal are performed under one of in situ and in vacuo conditions.  
     
     
         17 . The manufacturing method of a semiconductor device according to  claim 8 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.  
     
     
         18 . The manufacturing method of a semiconductor device according to  claim 9 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.  
     
     
         19 . The manufacturing method of a semiconductor device according to  claim 10 , wherein said low dielectric film is one selected from the group consisting of methyl silsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), silicon carbide (SiC), silicon oxycarbide or carbon-doped glass (SiOC or SiCOH), organo sillicated grass (OSG), silicon carbonitride (SiCN), and a porous film of any one of them.  
     
     
         20 . The manufacturing method of a semiconductor device according to  claim 8 , wherein a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment.  
     
     
         21 . The manufacturing method of a semiconductor device according to  claim 9 , wherein a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment.  
     
     
         22 . The manufacturing method of a semiconductor device according to  claim 10 , wherein a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment.  
     
     
         23 . The manufacturing method of a semiconductor device according to  claim 8 , wherein one of a noble gas and a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment, and RF bias is applied during said plasma treatment.  
     
     
         24 . The manufacturing method of a semiconductor device according to  claim 9 , wherein one of a noble gas and a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment, and RF bias is applied during said plasma treatment.  
     
     
         25 . The manufacturing method of a semiconductor device according to  claim 10 , wherein one of a noble gas and a mixed gas of hydrogen and a noble gas is used as a gas for said plasma treatment, and RF bias is applied during said plasma treatment.  
     
     
         26 . The manufacturing method of a semiconductor device according to  claim 20 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn..  
     
     
         27 . The manufacturing method of a semiconductor. device according to  claim 21 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.  
     
     
         28 . The manufacturing method of a semiconductor device according to  claim 22 , wherein-said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.  
     
     
         29 . The manufacturing method of a semiconductor device according to  claim 23 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.  
     
     
         30 . The manufacturing method of a semiconductor device according to  claim 24 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.  
     
     
         31 . The manufacturing method of a semiconductor device according to  claim 25 , wherein said noble gas includes one selected from the group consisting of He, Ne, Ar, Kr, Xe, and Rn.  
     
     
         32 . The manufacturing method of a semiconductor device according to  claim 23 , wherein, in a case where He is used as the gas for said plasma treatment, power of said RF bias is set to a range from 250 W to 400 W both inclusive.  
     
     
         33 . The manufacturing method of a semiconductor. device according to  claim 24 , wherein, in a case where He is used as the gas for said plasma treatment, power of said RF bias is set to. a range from 250 W to 400 W both inclusive.  
     
     
         34 . The manufacturing method of a semiconductor device according to  claim 25 , wherein, in a case where He is used as the gas for said plasma treatment, power of said RF bias is set to a range from 250 W to 400 W both inclusive.