Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film ( 6 ) and a second interlayer insulating film ( 4 ) formed of a low dielectric-constant film on a substrate, forming via holes ( 9 ) by using a first resist pattern ( 1 a ) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern ( 1 b ) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating ( 2 b ) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern ( 1 b ).

What is claimed is:  
     
         1 . A semiconductor device manufacturing method comprising a step of conducting a wet treatment using organic peeling liquid or cleaning liquid on a substrate having an insulating film formed thereon and then forming a resist pattern on the insulating film, characterized in that before a resist serving as the resist pattern or antireflection coating provided between the insulating film and the resist is coated subsequently to the wet treatment, a pre-treatment for removing reaction inhibiting materials which are contained in the organic peeling liquid or the cleaning liquid and inhibit the chemical reaction of the resist is conducted.  
     
     
         2 . The semiconductor device manufacturing method as claimed in  claim 1 , wherein the insulating film comprises a low dielectric-constant film.  
     
     
         3 . A semiconductor device manufacturing method comprising: at least a step of successively depositing at least a first interlayer insulating film and a second interlayer insulating film on a substrate on which a wiring pattern is formed; a step of forming a first resist pattern on the second interlayer insulating film and forming via holes by dry etching using the first resist pattern as a mask so that the via holes penetrate through the first interlayer insulating film and the second interlayer insulating film; a step of conducting at least one wet treatment of a treatment of removing etching residual materials with organic peeling liquid and a treatment of cleaning with cleaning liquid; a step of forming a second resist pattern on the second interlayer insulating film; a step of etching the second interlayer insulating film by using the second resist pattern as a mask to form wiring trench patterns; and a step of embedding wiring material in the via holes and the wiring trench patterns and polishing the surface of the wiring material thus embedded to thereby form a wiring pattern, characterized in that before a resist serving as the second resist pattern or antireflection coating provided between the second insulating film and the resist is coated subsequently to the wet treatment, a pre-treatment for removing reaction inhibiting materials which are contained in the organic peeling liquid or the cleaning liquid and inhibit the chemical reaction of the resist is conducted.  
     
     
         4 . A semiconductor device manufacturing method comprising: at least a step of depositing at least a first interlayer insulating film, a second interlayer insulating film and a mask member formed of inorganic material; a step of forming a first resist pattern on the mask member and etching the mask member by using the first resist pattern to form a hard mask; a step of conducting at least one wet treatment of a treatment for removing etching residual materials with organic peeling liquid and a treatment for cleaning with cleaning liquid; a step of forming a second resist pattern on the hard mask; a step of forming via holes by using dry etching using the second resist pattern as a mask so that the via holes penetrate through the first interlayer insulating film and the second interlayer insulating film; a step of etching the second interlayer insulating film by using the hard mask to form wiring trench patterns after the second resist pattern is removed; and a step of embedding wire material into the via holes and the wiring trench patterns and polishing the surface of the wiring material to form a wiring pattern, characterized in that before a resist serving as the second resist pattern or antireflection coating provided between the second insulating film and the resist is coated subsequently to the wet treatment, a pre-treatment for removing reaction inhibiting materials which are contained in the organic peeling liquid or the cleaning liquid and inhibit the chemical reaction of the resist is conducted.  
     
     
         5 . The semiconductor device manufacturing method as claimed in  claim 3  or  4 , wherein at least one of the first interlayer insulating film and the second interlayer insulating film is formed of a low dielectric-constant film.  
     
     
         6 . The semiconductor device manufacturing method as claimed in any one of claims  1 ,  3  and  4 , wherein the reaction inhibiting materials comprise basic materials so that catalysis action of acid occurring in the resist due to light exposure is inhibited by the basic materials.  
     
     
         7 . The semiconductor device manufacturing method as claimed in  claim 6 , wherein the basic materials contain amine.  
     
     
         8 . The semiconductor device manufacturing method as claimed in any one of claims  1 ,  3  or  4 , wherein at least one of an annealing treatment, a UV treatment, a plasma treatment and an organic solvent treatment is carried out as the pre-treatment.  
     
     
         9 . The semiconductor device manufacturing method as claimed in  claim 8 , wherein as the pre-treatment is carried out the UV treatment after the annealing treatment.  
     
     
         10 . The semiconductor device manufacturing method as claimed in  claim 8 , wherein the annealing treatment comprises a treatment for conducting annealing at a predetermined temperature to eliminate the reaction inhibiting materials infiltrated into or adsorbed to the insulating film, the first interlayer insulating film or the second interlayer insulating film.  
     
     
         11 . The semiconductor device manufacturing method as claimed in  claim 10 , wherein the annealing treatment is carried out in a temperature range from 150° C. to 450° C.  
     
     
         12 . The semiconductor device manufacturing method as claimed in  claim 11 , wherein the annealing treatment is carried out at a temperature higher than the bake temperature of the antireflection coating or the resist.  
     
     
         13 . The semiconductor device manufacturing method as claimed in  claim 10 , wherein the annealing treatment is carried out under a pressure-reduced condition, under nitrogen gas atmosphere, under inert gas atmosphere, or under hydrogen atmosphere.  
     
     
         14 . The semiconductor device manufacturing method as claimed in  claim 8 , wherein the UV treatment comprises a treatment for neutralizing the reaction inhibiting materials infiltrated into or adsorbed to the insulating film, the first interlayer insulating film or the second interlayer insulating film with oxygen or ozone activated by irradiation of UV light.  
     
     
         15 . The semiconductor device manufacturing method as claimed in  claim 8 , wherein the plasma treatment comprises a treatment for etching the reaction inhibiting materials infiltrated into or adsorbed to the insulating film, the first interlayer insulating film or the second interlayer insulating film with plasma containing at least one of oxygen, nitrogen and ammonia.  
     
     
         16 . The semiconductor device manufacturing method as claimed in  claim 8 , wherein the organic solvent treatment uses organic solvent containing any one of polypyreneglycol monomethyl ether acetate, polypyreneglycol monomethyl ether, ethyl lactate, cyclohexanone and methyl ethyl ketone.  
     
     
         17 . The semiconductor device manufacturing method as claimed in  claim 16 , wherein the organic solvent contains acidic material so that the reaction inhibiting materials infiltrated into or adsorbed to the insulating film, the first interlayer insulating film or the second interlayer insulating film are neutralized by the acidic material.  
     
     
         18 . The semiconductor device manufacturing method as claimed in  claim 16 , wherein the organic solvent contains weakly basic material so that the reaction inhibiting materials infiltrated into or adsorbed to the insulating film, the first interlayer insulating film or the second interlayer insulating film are substituted into the weakly basic materials.  
     
     
         19 . A semiconductor device manufactured by the method as claimed in m)any one of claims  1 ,  3  and  4 , wherein at least one of an annealing treatment and a UV treatment is used as the pre-treatment, and the device comprises the wiring pattern formed in the via holes or the wiring trench patterns and having a side wall, and the insulating film having a face layer portion contacting at least a portion of the side wall of the wiring pattern and an inner portion other than the face layer portion, the face layer portion having a composition ratio or density which is different from that of the inner portion.  
     
     
         20 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and an interlayer insulating film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the interlayer insulating film contains Si and O as a predominant element and the face layer portion is lower in nitrogen concentration than the inner portion.  
     
     
         21 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a low dielectric constant interlayer insulating film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the interlayer insulating film contains Si, O and H as a predominant element and the face layer portion is higher in oxygen concentration and lower in hydrogen concentration than the inner portion.  
     
     
         22 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 21 , wherein the face layer portion has a distribution in concentration in which the oxygen concentration is highest and the hydrogen concentration is lowest at the outer surface thereof and the oxygen concentration is gradually reduced and the hydrogen concentration is gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         23 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a low dielectric constant interlayer insulating film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the interlayer insulating film contains Si, O, C and H as a predominant element and the face layer portion is higher in oxygen concentration and lower in carbon and hydrogen concentrations than the inner portion.  
     
     
         24 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 23 , wherein the face layer portion has a distribution in concentration in which the oxygen concentration is highest and the carbon and hydrogen concentrations are lowest at the outer surface thereof and the oxygen concentration is gradually reduced and the carbon and hydrogen concentrations are gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         25 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a barrier film or an etching stop film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the barrier film or the etching stop film contains Si, C, N and H as a predominant element and the face layer portion is higher in oxygen concentration and lower in carbon, nitrogen and hydrogen concentrations than the inner portion.  
     
     
         26 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 25 , wherein the face layer portion has a distribution in concentration in which the oxygen concentration is highest and the carbon, nitrogen and hydrogen concentrations are lowest at the outer surface thereof and the oxygen concentration is gradually reduced and the carbon, nitrogen and hydrogen concentrations are gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         27 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a barrier film or an etching stop film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the barrier film or the etching stop film contains Si, C and H as a predominant element and the face layer portion is higher in oxygen concentration and lower in carbon and hydrogen concentrations than the inner portion.  
     
     
         28 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 27 , wherein the face layer portion has a distribution in concentration in which the oxygen concentration is highest and the carbon and hydrogen concentrations are lowest at the outer surface thereof and the oxygen concentration is gradually reduced and the carbon and hydrogen concentrations are gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         29 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a low dielectric constant interlayer insulating film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the interlayer insulating film contains Si, O and H or alternatively Si, O, C and H as a predominant element and the face layer portion is higher in density than the inner portion.  
     
     
         30 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a barrier film or an etching stop film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the barrier film or the etching stop film contains Si, C, N and H or alternatively Si, C and H as a predominant element and the face layer portion is higher in density than the inner portion.  
     
     
         31 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 29  or  30 , wherein the face layer portion has a distribution in density in which the density is highest at the outer surface thereof and gradually reduced toward the inner portion to approach to that of the inner portion.  
     
     
         32 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a low dielectric constant interlayer insulating film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the interlayer insulating film contains Si, O and H as a predominant element and the face layer portion is higher in a ratio of Si—O bond and lower in a ratio of Si—H bond than the inner portion.  
     
     
         33 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 32 , wherein the face layer portion has a distribution in bond ratio in which the Si—O bond ratio is highest and the Si—H bond ratio is lowest at the outer surface thereof and the Si—O bond ratio is gradually reduced and the Si—H bond ratio is gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         34 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a low dielectric constant interlayer insulating film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the interlayer insulating film contains Si, O, C and H as a predominant element and the face layer portion is higher in a ratio of Si—O bond and lower in a ratio of Si—CH 3  bond than the inner portion.  
     
     
         35 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 34 , wherein the face layer portion has a distribution in bond ratio in which the Si—O bond ratio is highest and the Si—CH 3  bond ratio is lowest at the outer surface thereof and the Si—O bond ratio is gradually reduced and the Si—CH 3  bond ratio is gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         36 . A semiconductor device having a dual damascene wiring structure, comprising at least one of a via and a wire made of conductive material having a side wall, and a barrier film or an etching stop film having a face layer portion contacting at least a portion of the side wall of the via or the wire and an inner portion other than the face layer portion, wherein the barrier film or the etching stop film contains Si, C, N and H or alternatively Si, C and H as a predominant element and the face layer portion is lower in a ratio of Si—CH 3  bond than the inner portion.  
     
     
         37 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 36 , wherein the face layer portion has a distribution in bond ratio in which a Si—O bond ratio is highest and the Si—CH 3  bond ratio is lowest at the outer surface thereof and the Si—O bond ratio is gradually reduced and the Si—CH 3  bond ratio is gradually increased toward the inner portion to approach to those of the inner portion.  
     
     
         38 . The semiconductor device having a dual damascene wiring structure as claimed in any one of  claims 20  to  30  and  32  to  37 , wherein the thickness of the face layer portion is substantially 30 nm or less.  
     
     
         39 . The semiconductor device having a dual damascene wiring structure as claimed in any one of claims  21 ,  22 ,  29 ,  32  and  33 , wherein the low dielectric constant interlayer insulating film containing Si, O and H as a predominant element is ladder hydrogenated siloxane.  
     
     
         40 . The semiconductor device having a dual damascene wiring structure as claimed in  claim 39 , wherein L-Ox (registered trademark) is used as the ladder hydrogenated siloxane.