US2004155241A1PendingUtilityA1

Test assembly for integrated circuit package

33
Assignee: ADVANCED SEMICONDUCTOR ENGPriority: Apr 15, 2002Filed: Feb 10, 2004Published: Aug 12, 2004
Est. expiryApr 15, 2022(expired)· nominal 20-yr term from priority
G01R 1/0408G01R 31/305
33
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Claims

Abstract

A test assembly for an integrated circuit package includes a package substrate and a test board. The package substrate is provided with a plurality of first contact pads linked in a first daisy chain pattern. The test board has a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads. All of the second contact pads are divided into a plurality of groups each connected to one pair of test pads. All of the second contact pads in any group are arranged in a line. The present invention further provides a method of testing an integrated circuit package utilizing the aforementioned package substrate and test board.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A test assembly for an integrated circuit package, the test assembly comprising: 
 a package substrate having a plurality of first contact pads linked in a first daisy chain pattern; and    a test board having a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads, all of the second contact pads being divided into a plurality of groups each connected to one pair of test pads wherein all of the second contact pads in any group are arranged in a line,    wherein all of the second contact pads in any group are in a series electrical connection to one another through the first and second daisy chain patterns when the package substrate is mounted on the test board, and all of the second contact pads in any group form a closed circuit when the corresponding pair of test pads are probed.    
     
     
         2 . The test assembly as claimed in  claim 1 , wherein the test board comprises a pair of major test pads such that all of the second contact pads form a closed circuit when the pair of major test pads is probed.  
     
     
         3 . The test assembly as claimed in  claim 1 , wherein the package substrate is a ball grid array substrate.  
     
     
         4 . A method of testing an integrated circuit package having a substrate with a plurality of first contact pads linked in a first daisy chain pattern, the method comprising: 
 providing a test board having a plurality of second contact pads linked in a second daisy chain pattern and a plurality of test pads, all of the second contact pads being divided into a plurality of groups each connected to one pair of test pads wherein all of the second contact pads in any group are arranged in a line;    mounting the integrated circuit package on the test board by reflowing solder bumps provided on the integrated circuit package to the second contact pads of the test board wherein all of the second contact pads in any group are in a series electrical connection to one another through the first and second daisy chain patterns; and    performing an electrical test after conducting the mounting step,    wherein all of the second contact pads in any group form a closed circuit when the corresponding pair of test pads are probed.    
     
     
         5 . The method as claimed in  claim 4 , wherein the test board comprises a pair of major test pads such that all of the second contact pads form a closed circuit when the pair of major test pads is probed.

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