Conformal thin films over textured capacitor electrodes

Abstract

Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

We claim:  
     
         1 . A capacitor structure in an integrated circuit, comprising: 
 a bottom electrode conforming to a macrostructural three-dimensional folding shape and having a textured silicon surface; and    an ALD-deposited capacitor dielectric having a dielectric constant greater than about 10 conforming to the textured surface, the dielectric having a maximum thickness of X, wherein X is a single numerical value being less than about 100 Å and at all points over the bottom electrode the capacitor dielectric has a minimum thickness of at least about 0.95 times X, wherein the dielectric comprises a compound including a transition metal.    
     
     
         2 . The structure of  claim 1. , further comprising a top electrode conforming to the dielectric, the top electrode continuously contacting the dielectric over the entire textured surface.  
     
     
         3 . The structure of  claim 2 , wherein the top electrode comprises a conductive barrier layer continuously contacting the dielectric over the entire textured surface and a more conductive material formed over the conductive barrier layer.  
     
     
         4 . The structure of  claim 2 , wherein the top electrode comprises an elemental metal layer continuously contacting the dielectric over the entire textured surface.  
     
     
         5 . The structure of  claim 1 , wherein the capacitor dielectric comprises a metal oxide.  
     
     
         6 . The structure of  claim 7 , wherein the dielectric further comprises aluminum oxide.  
     
     
         7 . The structure of  claim 5 , wherein the metal oxide comprises an oxide of the transition metal.  
     
     
         8 . The structure of  claim 7 , further comprising a conformal barrier layer formed between the textured silicon layer and the dielectric.  
     
     
         9 . The structure of  claim 7 , wherein the metal oxide layer comprises an oxide of a Group IV transition metal.  
     
     
         10 . The structure of  claim 7 , wherein the metal oxide comprises an oxide of a Group V transition metal.  
     
     
         11 . The structure of  claim 1 , wherein the dielectric comprises a ternary material.  
     
     
         12 . The structure of  claim 11 , wherein the dielectric comprises a metal, silicon and oxygen.  
     
     
         13 . The structure of  claim 1 , wherein the maximum thickness X of the capacitor dielectric is between about 25 Å and 100 Å.  
     
     
         14 . The structure of  claim 1 , wherein at all points over the bottom electrode the capacitor dielectric has a minimum thickness of at least about 0.98 times X.