Method of generating multiple oxides by plasma nitridation on oxide

Abstract

A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N 2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

We claim:  
     
         1 . A method of forming three different gate oxide thicknesses on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed,    (b) growing a first oxide layer on said substrate,    (c) removing selected portions of first oxide layer,    (d) growing a second oxide layer on said substrate, and    (e) nitridating selected portions of the second oxide layer.    
     
     
         2 . The method of  claim 1  wherein the isolation regions are shallow trench isolation features in a silicon substrate.  
     
     
         3 . The method of  claim 1  wherein the first oxide growth is performed in an oxidation furnace with a dry oxygen ambient at a temperature of between 600° C. and 800° C. and the oxide layer is silicon dioxide grown to a thickness of between 50 and 60 Angstroms and preferably about 50 Angstroms.  
     
     
         4 . The method of  claim 1  wherein selected portions of first oxide layer are removed by patterning a photoresist on said substrate and removing the exposed oxide layer with a dilute HF etchant.  
     
     
         5 . The method of  claim 1  further comprised of an annealing step after step (c), said annealing is accomplished in a chamber containing N 2 flowing at a rate of between 5 and 10 standard liters per minute (slm) and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. with a total chamber pressure between about 10 and 100 Torr for a period of 30 to 120 seconds.  
     
     
         6 . The method of  claim 1  wherein the second oxide growth is performed in an oxidation furnace with a dry oxygen ambient at a temperature of between 600° C. and 800° C. and the oxide layer is silicon dioxide grown to a thickness of between 20 and 30 Angstroms and preferably about 22 Angstroms.  
     
     
         7 . The method of  claim 1  wherein the nitridation is performed by patterning a photoresist on said substrate to expose selected portions of said second oxide layer and then nitridating said substrate in a chamber with a N 2  flow rate of 100 sccm, a pressure of 1.5 Torr, and a power of 300 Watts for a period of 30 to 300 seconds at a temperature less than 100° C. and preferably 25° C.  
     
     
         8 . The method of  claim 1  wherein an annealing step is performed after step (e), said annealing is accomplished in a chamber containing N 2 flowing at a rate of between 5 and 10 slm and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. with a chamber pressure of between about 10 and 100 Torr for 30 to 120 seconds.  
     
     
         9 . The method of  claim 1  wherein the thicker oxide layer is used to make a MOSFET which is part of an I/O device circuit and the thinner oxide layers are used to make MOSFETs which are part of low power and high performance device circuits.  
     
     
         10 . A method of forming four different gate oxide thicknesses on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed,    (b) growing a first oxide layer on said substrate,    (c) removing selected portions of first oxide layer,    (d) growing a second oxide layer on said substrate, and    (e) nitridating selected portions of said first and second oxide layers.    
     
     
         11 . The method of  claim 10  wherein the isolation regions are shallow trench isolation features in a silicon substrate.  
     
     
         12 . The method of  claim 10  wherein the first oxide growth is performed in an oxidation furnace with a dry oxygen ambient at a temperature of between 600° C. and 800° C. and the oxide layer is silicon dioxide grown to a thickness of between 50 and 60 Angstroms and preferably about 50 Angstroms.  
     
     
         13 . The method of  claim 10  wherein selected portions of first oxide layer are removed by patterning a photoresist on said substrate and removing exposed oxide layer with a dilute HF etchant.  
     
     
         14 . The method of  claim 10  further comprised of an annealing step after step (c), said annealing is accomplished in a chamber containing N 2 flowing at a rate of between 5 and 10 slm and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. with a total chamber pressure of between about 10 and 100 Torr for 30 to 120 seconds.  
     
     
         15 . The method of  claim 10  wherein the second oxide growth is performed in an oxidation furnace with a dry oxygen ambient at a temperature of between 600° C. and 800° C. and the oxide layer is silicon dioxide grown to a thickness of between 20 and 30 Angstroms and preferably about 20 Angstroms.  
     
     
         16 . The method of  claim 10  wherein the nitridation is performed by patterning a photoresist on said substrate to expose selected portions of said first and second oxide layers and then nitridating said substrate in a chamber with a N 2  flow rate of 100 sccm, a pressure of 1.5 Torr, and a power of 300 Watts for a period of 30 to 300 seconds at a temperature less than 100° C. and preferably 25° C.  
     
     
         17 . The method of  claim 10  wherein an annealing step is performed after step (e), said annealing is accomplished in a chamber containing N 2 flowing at a rate of between 5 and 10 slm and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. with a chamber pressure between about 10 and 100 Torr for a period of 30 to 120 seconds.  
     
     
         18 . The method of  claim 10  wherein at least one of the two thicker oxide layers is used to make a MOSFET which is part of an I/O device circuit and the thinner oxide layers are used to make MOSFETs which are part of low power and high performance device circuits.  
     
     
         19 . A method of forming four different gate oxide thicknesses on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed,    (b) growing an oxide layer on said substrate,    (c) reducing the thickness of selected portions of said oxide layer to provide a second oxide layer with a thinner thickness than the first oxide layer, and    (d) nitridating selected portions of said first and second oxide layers.    
     
     
         20 . The method of  claim 19  wherein the isolation regions are shallow trench isolation features in a silicon substrate.  
     
     
         21 . The method of  claim 19  wherein the oxide growth is performed in an oxidation furnace with a dry oxygen ambient at a temperature of between 600° C. and 800° C. and the oxide layer is silicon dioxide grown to a thickness of between 50 and 60 Angstroms and preferably about 50 Angstroms.  
     
     
         22 . The method of  claim 19  wherein selected portions of first oxide layer are thinned by patterning a photoresist on said substrate and etching the exposed oxide layer with a dilute HF etchant for about 5 to 10 seconds.  
     
     
         23 . The method of  claim 19  wherein the nitridation is performed by patterning a photoresist on said substrate to expose selected portions of said first and second oxide layers and then nitridating said substrate in a chamber with a N 2  flow rate of 100 sccm, a pressure of 1.5 Torr, and a power of 300 Watts for a period of 30 to 120 seconds at a temperature less than 100° C. and preferably 25° C.  
     
     
         24 . The method of  claim 19  wherein an annealing step is performed after step (d), said annealing is accomplished in a chamber containing N 2 flowing at a rate of between 5 and 10 slm and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. with a chamber pressure of between about 10 and 100 Torr for 30 to 120 seconds.  
     
     
         25 . The method of  claim 19  wherein at least one portion of the thicker oxide layer is used to make a MOSFET which is part of an I/O device circuit and the thinner oxide layer is used to make MOSFETs which are part of low power and high performance device circuits.  
     
     
         26 . A method of forming three different gate oxide thicknesses on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed, with one said active area having a nitrogen implant near the substrate surface,    (b) growing a first oxide layer on active areas of said substrate,    (c) removing selected portions of first oxide layer including the oxide over the nitridated active area,    (d) growing a second oxide layer on active areas of said substrate,    (e) annealing said substrate,    (f) nitridating all oxide regions, and    (g) annealing said substrate.    
     
     
         27 . The method of  claim 26  wherein the first oxide is comprised of a HfO 2 /silicate layer which is formed by first growing a SiO 2  layer with a thickness of about 3 Angstroms using an RTO method followed by depositing a HfO 2  layer with a thickness in a range of 20 to 30 Angstroms and preferably 25 Angstroms.  
     
     
         28 . The method of  claim 26  wherein selected portions of the HfO 2 /silicate layer are removed by patterning a photoresist on said substrate and then etching exposed HfO 2 /silicate layer with a dilute HF solution.  
     
     
         29 . The method of  claim 26  wherein a second oxide layer is grown by an RTO method at a temperature of 650° C. to give a thickness of about 10 Angstroms on active areas with a nitrogen implant and a thickness of about 15 Angstroms on active areas with no nitrogen implant.  
     
     
         30 . The method of  claim 26  wherein annealing steps are accomplished in a chamber containing N 2  flowing at a rate of between 5 and 10 slm and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. and a chamber pressure of between about 10 and 100 Torr for a period of 30 to 120 seconds.  
     
     
         31 . The method of  claim 26  wherein the nitridation is performed by placing said substrate in a chamber with a N 2  flow rate of 100 sccm, a pressure of 1.5 Torr, and a power of 300 Watts for a period of 30 to 300 seconds at a temperature less than 100° C. and preferably 25° C.  
     
     
         32 . The method of  claim 26  wherein the HfO 2 /silicate layer is used to make a integrated circuit with DRAM functionality, the thicker SiO 2  gate oxide is used to make a MOSFET which is art of a low power logic circuit, and the thinner SiO 2  gate oxide is used to make a MOSFET as part of a high performance logic circuit.  
     
     
         33 . An article that is useful for providing a microelectronic or MEMS device with increased resistance to migration of impurity dopants between a gate electrode and a channel region in an integrated circuit and which reduces leakage of standby current in said devices, said article comprising a gate oxide layer which contains nitrogen that has been introduced by a nitrogen plasma or with a nitrogen implant process.  
     
     
         34 . The article of  claim 33  wherein the oxide layer has been grown in an oxidation furnace with a dry oxygen ambient at a temperature of between 600° C. and 800° C. and the oxide layer is SiO 2  grown to a thickness of between 20 and 20 Angstroms.  
     
     
         35 . The article of  claim 33  wherein the nitridation is performed in a chamber with a N 2  flow rate of 100 sccm, a pressure of 1.5 Torr, and a power of 300 Watts for a period of 30 to 120 seconds at a temperature less than 100° C. and preferably 25° C.  
     
     
         36 . The artide of  claim 33  wherein an annealing step is performed after the introduction of nitrogen into the oxide layer, said annealing is accomplished in a chamber containing N 2 flowing at a rate of between 5 and 10 slm and He flowing at a rate of between about 5 and 10 slm while the surface of said substrate is heated to a temperature of between about 900° C. and 1200° C. with a total chamber pressure of between about 10 and 100 Torr for a period of 30 to 120 seconds.  
     
     
         37 . The article of  claim 29  wherein the oxide layer is HfO 2  or HfO 2 /silicate with a thickness of between 20 and 30 Angstroms and preferably about 25 Angstroms.  
     
     
         38 . A method of forming a first MOSFET with a first gate oxide thickness, a second MOSFET with a second oxide thickness, and a third MOSFET with a third oxide thickness on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed,    (b) growing a first oxide layer on said substrate,    (c) removing selected portions of said first oxide layer,    (d) growing a second oxide layer on said substrate,    (e) nitridating selected portions of said second oxide layer,    (f) forming a gate electrode over each of said oxide layers, and    (g) forming source/drain elements in said active areas, and    (h) forming contacts to said source/drain elements and to the gate electrodes, thereby forming first, second, and third MOSFETs.    
     
     
         39 . A method of forming a first MOSFET with a first gate oxide thickness, a second MOSFET with a second oxide thickness, a third MOSFET with a third oxide thickness and a fourth MOSFET with a fourth oxide thickness on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed,    (b) growing an oxide layer on said substrate,    (c) reducing the thickness of selected portions of said oxide layer to form a second oxide layer with a thinner thickness,    (d) nitridating selected portions of said first and second oxide layers,    (e) forming a gate electrode over each of said oxide layers,    (f) forming source/drain elements in said active areas, and    (g) forming contacts to said source/drain elements and to the gate electrodes, thereby forming first, second, third, and fourth MOSFETs.    
     
     
         40 . A method of forming a DRAM circuit with a first gate oxide thickness, a first MOSFET with a second oxide thickness, and a second MOSFET with a third oxide thickness on a substrate comprising: 
 (a) providing a substrate with isolation regions that separate active areas where circuits are to be formed, one active area having a nitrogen implant    (b) growing an oxide layer on said substrate,    (c) removing selected portions of first oxide layer induding the oxide over the nitridated active area,    (d) growing a second oxide layer on said substrate,    (e) nitridating all oxide layers,    (f) annealing said substrate,    (g) forming a gate electrode over each of said oxide layers, and    (h) forming source/drain elements in said active areas, and    (i) forming contacts to source/drain elements and to the gate electrodes, thereby forming a DRAM circuit and first and second MOSFETs.