Apparatus for evaluating lithography process margin simulating layout pattern of semiconductor device

Abstract

A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

1 - 6 . (Canceled)  
     
     
         7 . A lithography process margin evaluating program product to be executed by a computer used in a lithography process margin evaluating apparatus, simulating, a light intensity distribution within a photosensitive material on a semiconductor substrate and an actual layout pattern formed on said semiconductor substrate using a design layout pattern formed on a mask, comprising the steps of: 
 selecting a design layout pattern template from a layout pattern template holding unit storing a plurality of design layout pattern templates, and generating a plurality of design layout patterns based on an analysis condition entered for analyzing said actual layout pattern and said selected design layout pattern template;    selecting a simulation condition template from a simulation condition template holding unit storing a plurality of simulation condition templates, and generating a plurality of simulation conditions based on said analysis condition and said selected simulation condition template;    simulating an actual layout pattern transferred to the photosensitive material on the semiconductor substrate, using said plurality of design layout patterns and said plurality of simulation conditions;    determining a measuring condition from a measuring condition holding unit storing a plurality of measuring conditions for measuring said actual layout pattern based on said analysis condition; and    measuring said actual layout pattern with said determined measuring condition.    
     
     
         8 . The lithography process margin evaluating program product according to  claim 7 , further comprising the step of 
 analyzing said actual layout pattern, using said analysis condition and a measurement result from said step of measuring.    
     
     
         9 . The lithography process margin evaluating program product according to  claim 8 , wherein 
 in said step of simulating, a test layout pattern is simulated, using a prescribed design layout pattern and a prescribed simulation condition prior to simulation based on said analysis condition,    in said step of measuring, said test layout pattern is measured with a prescribed measuring condition, and    in said step of analyzing, a reference light intensity value is determined, using a measurement result from said measuring unit.    
     
     
         10 . The lithography process margin evaluating program product according to  claim 8 , wherein 
 said step of generating a plurality of design layout patterns includes the steps of 
 generating a plurality of design layout patterns based on said analysis condition and said selected design layout pattern template, and  
 generating a plurality of corrected layout patterns by performing optical proximity correction of said plurality of design layout patterns.  
   
     
     
         11 . The lithography process margin evaluating program product according to  claim 10 , wherein 
 in said step of generating a plurality of corrected layout patterns, said plurality of corrected layout patterns are generated for each design layout pattern, and    in said step of analyzing, one is selected from said plurality of corrected layout patterns for said each design layout pattern based on said analysis condition.    
     
     
         12 . The lithography process margin evaluating program product according to  claim 8 , further comprising the step of 
 converting data of said design layout pattern generated in said step of generating a plurality of layout patterns to data usable in a manufacturing apparatus.