Manufacturing method for multichip module

Abstract

A manufacturing method for a multi-chip module is provided, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. An adhesive with fillers allows a second chip to be superimposed over a first chip after the first chip is electrically connected to the chip carrier. The diameter of the fillers is higher than loop height of the bonding wires that are positioned above the active surface of the first chip to prevent the bonding wires to come in contact with the second chip. Moreover, the other embodiment of the fillers (such as copper or aluminum) with high thermal conductivity is also capable of enhancing heat dissipation of the stacked package application.

1 - 16 . (canceled)  
   
   
       17 . A manufacturing method of the multichip module, comprising the steps of: 
 preparing a chip carrier;    adhering at least one first chip, having an active surface and a non-active surface, to the chip carrier;    using a plurality of first bonding wires for electrically connecting the active surface of the first chip to the chip carrier;    applying an adhesive layer on the active surface of the first chip, the adhestive layer comprising a plurality of fillers, each having a diameter larger than a loop height of each of the plurality of first bonding wires;    adhering at least one second chip to the first chip, in which the thickness of the fillers between the first chip and the second chip is larger than the loop height of the first bonding wires;    using a plurality of second bonding wires for electrically connecting the second chip to the chip carrier; and    encapsulating the first chip, the first bonding wires, the second chip, and the second bonding wires by an encapsulant.    
   
   
       18 . The manufacturing method of the multichip module of  claim 17 , wherein the multichip module is a stacked semiconductor package.  
   
   
       19 . The manufacturing method of the multichip module of  claim 17 , wherein the chip carrier is a substrate.  
   
   
       20 . The manufacturing method of the multichip module of  claim 17 , wherein the chip carrier is a leadframe.  
   
   
       21 . The manufacturing method of the multichip module of  claim 17 , wherein the first bonding wires are bonded using reverse bonding technique.  
   
   
       22 . The manufacturing method of the multichip module of  claim 21 , wherein a plurality of studs are formed on the active surface of the first chip prior to the bonding of the first bonding wires using reverse bonding technique.  
   
   
       23 . The manufacturing method of the multichip module of  claim 17 , wherein the adhesive is applied over the first chip using print screening technique.  
   
   
       24 . The manufacturing method of the multichip module of  claim 17 , wherein the adhesive layer is formed with a plurality of fillers mixing evenly within an adhesive substrate.  
   
   
       25 . The manufacturing method of the multichip module of  claim 17 , wherein the adhesive substrate is a dielectric adhesive.  
   
   
       26 . The manufacturing method of the multichip module of  claim 17 , wherein the adhesive substrate is a conductive adhesive.  
   
   
       27 . The manufacturing method of the multichip module of  claim 17 , wherein the adhesive substrate is made of a material selected from a group consisting of epoxy resin and polyimide.  
   
   
       28 . The multichip module of  claim 17 , wherein the fillers are made of a material selected from copper, aluminum, copper alloys, aluminum alloys, carbon silicon compound and silicon.  
   
   
       29 . The multichip module of  claim 17 , wherein the fillers are made of a dielectric material of high molecular polymers.  
   
   
       30 . The multichip module of  claim 17 , wherein the fillers are made of a conductive and rigid material.  
   
   
       31 . The multichip module of  claim 17 , wherein the fillers are further encapsulated with a dielectric thin layer.  
   
   
       32 . The multichip module of  claim 17 , wherein the thickness of the adhesive layer is determined by the diameter of the fillers.  
   
   
       33 . The multichip module of  claim 17 , wherein the diameter of the fillers is larger than the loop height of the first bonding wires.  
   
   
       34 . The multichip module of  claim 17 , wherein the loop height of the first bonding wires is defined by the distance between the active surface of the first chip and the vertexes of the outwardly projecting loops of the first bonding wires.