Locos trench isolation structure

Abstract

A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.

1 . An isolation structure in a semiconductor structure that includes a pad oxide layer upon a semiconductor substrate and an oxidation barrier layer upon the pad oxide layer, wherein the oxidation barrier layer has a lateral surface thereon, the isolation structure comprising: 
 a trench extending between the oxidation barrier layer and a field oxide region in the semiconductor substrate, the trench being filled with a dielectric material comprising a nitride; and    a spacer comprising a dielectric material and situated on the lateral surface of the oxidation barrier layer.    
   
   
       2 . The isolation structure of  claim 1 , further comprising a dopant at a bottom of the trench.  
   
   
       3 . The isolation structure of  claim 1 , wherein: 
 the semiconductor substrate has a top surface;    the trench extends within the semiconductor substrate below the top surface of the semiconductor substrate; and    the trench has a maximum width of less than about 2,000 Å at an intersection with the top surface of the semiconductor substrate.    
   
   
       4 . The isolation structure of  claim 1 , wherein the trench has a depth in a range from about 0.1 microns to about 1 micron.  
   
   
       5 . The isolation structure of  claim 1 , wherein: 
 the trench has a maximum width at an intersection thereof with the top surface of the semiconductor substrate that is in a range from about 50 Å to about 10,000 Å.    
   
   
       6 . The isolation structure of  claim 3 , wherein: 
 the intersection of the trench with the top surface of the semiconductor substrate has a first edge opposite a second edge;    the field oxide region is in contact with the first edge; and    a gate oxide layer is in contact with the second edge.    
   
   
       7 . An isolation structure in a semiconductor structure that includes a pad oxide layer upon a semiconductor substrate having a top surface and an oxidation barrier layer upon the pad oxide layer, wherein the oxidation barrier layer has a lateral surface thereon, the isolation structure comprising: 
 a trench extending between the oxidation barrier layer and a field oxide region in the semiconductor substrate, the trench being filled with a first dielectric material comprising a nitride; and    a spacer composed of a second dielectric material, different than the first dielectric material, and situated on the lateral surface of the oxidation barrier layer.    
   
   
       8 . The isolation structure of  claim 7 , wherein the second dielectric material comprises an oxide.  
   
   
       9 . The isolation structure of  claim 7 , further comprising a dopant at a bottom of the trench.  
   
   
       10 . The isolation structure of  claim 7 , wherein: 
 the trench extends within the semiconductor substrate below the top surface of the semiconductor substrate; and    the trench has a maximum width of less than about 2,000 Å at an intersection with the top surface of the semiconductor substrate.    
   
   
       11 . The isolation structure of  claim 7 , wherein the first dielectric material extends above the top surface of the semiconductor substrate.  
   
   
       12 . An isolation structure comprising: 
 a semiconductor substrate having first and second separate active regions each extending to a top surface of the semiconductor substrate;    a field oxide region having a convex top surface opposite a convex bottom surface, wherein: 
 the convex bottom surface extends within the semiconductor substrate below the top surface of the semiconductor substrate to a first depth;  
 the field oxide region is separated from the first and second separate active regions; and  
 the convex top surface extends above the top surface of the semiconductor substrate;  
   a first isolation trench filled with a dielectric material comprising a nitride, extending into the semiconductor substrate, and having a first spacer formed thereto, the first spacer extending above the top surface of the semiconductor substrate, wherein: 
 the first isolation trench has first and second opposite sides;  
 the first side of the first isolation trench makes contact with the field oxide region; and  
 the second side of the first isolation trench makes contact with the first active region; and  
   a second isolation trench filled with a dielectric material comprising a nitride, extending into the semiconductor substrate, and having a second spacer formed thereto, the second spacer extending above the top surface of the semiconductor substrate, wherein: 
 the second isolation trench has first and second opposite sides;  
 the first side of the second isolation trench makes contact with the field oxide region; and  
 the second side of the second isolation trench makes contact with the second active region.  
   
   
   
       13 . An isolation structure, comprising: 
 a semiconductor substrate comprising a semiconductive material and having first and second separate active regions each extending to a top surface of the semiconductor substrate;    a field oxide region having opposite sides, a curved top surface, and a curved bottom surface, wherein: 
 the curved bottom surface projects within the semiconductor substrate below the top surface of the semiconductor substrate;  
 the field oxide region is separated from the first and second separate active regions; and  
 the curved top surface projects above the top surface of the semiconductor substrate;  
   a pair of nitride dielectric extensions each: 
 having opposite first and second sides;  
 projecting within and making contact with the semiconductive material of the semiconductor substrate below the top surface of the semiconductor substrate;  
 contacting a respective one of the active regions on the first side thereof;  
 being out of contact from one of the active regions on the second side thereof; and  
 projecting above the top surface of the semiconductor substrate; and  
   a pair of layers each of which: 
 is upon a respective one of the active regions; and  
 intersects a respective one of the dielectric extensions on one of the opposite sides of the field oxide region; wherein each of the dielectric extensions constitutes a structural barrier between the opposite first and second sides, thus preventing the contact with a respective one of the active regions and the field oxide region, and preventing the encroachment of material from the field oxide region into the respective active region.  
   
   
   
       14 . An isolation structure including a semiconductor substrate having a plurality of active regions extending to a top surface of the semiconductor substrate, the isolation structure comprising: 
 a pair of dielectric trench structures each of which contacts one of the active regions and comprises a nitride, the trench structures extending both below and above the top surface of the semiconductor substrate and respectively lower and higher than a field oxide region within the semiconductor substrate, wherein the field oxide region is physically separate from the plurality of active regions, is longer than it is high, and has opposite sides each of which makes contact with a respective one of the trench structures; and    oxide layers upon the active regions and making contact with the field oxide region.    
   
   
       15 . An isolation structure including a semiconductor substrate having a plurality of active regions and a top surface of the semiconductor substrate, the isolation structure comprising: 
 a pair of dielectric trench structures each of which: 
 has a top portion comprising a nitride upon a bottom portion comprising an oxide;  
 contacts one of the active regions;  
 extends below the top surface of the semiconductor substrate to a first depth; and  
 extends above the top surface of the semiconductor substrate to a first height;  
   a field oxide region extending into the semiconductor substrate to a second depth less than the first depth, wherein the field oxide region: 
 extends above the top surface of the semiconductor substrate to a second height;  
 is physically separate from the plurality of active regions;  
 is longer than it is high; and  
 has opposite sides each of which makes contact with the nitride of a respective one of the dielectric trench structures; and  
   oxide layers upon each of the active regions and making contact with the field oxide region.    
   
   
       16 . The isolation structure of  claim 15 , wherein the first height is greater than the second height.