Semiconductor device having a thin film capacitor and method for fabricating the same

Abstract

In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2 (0<x<1), (Zr y , Ti 1-y )O 2 (0<y<1), (Hf z , Ti 1-z )O 2 (O<z<l), (Zr k , Ti l , Hf m )O 2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.

1 - 14 . (Cancelled).  
   
   
       15 . A method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2  (0<x<1), (Zr y , Ti 1-y )O 2  (0<y<1), (Hf z , Ti 1-z )O 2  (0<z<1), (Zr k , Ti l , Hf m )O 2  (0<k, l, m<1, k+l+m=1), and, forming an upper electrode of said capacitor on the capacitor dielectric film, so that the capacitor is constituted of said lower electrode, said capacitor dielectric film and said upper electrode, wherein at a stage after formation of said capacitor dielectric film, a heat treatment is carried out at a temperature not lower than a film deposition temperature in the atomic layer deposition.  
   
   
       16 . A method for fabricating a semiconductor device including a transistor having a gate electrode and source/drain diffused layers having a silicide of a refractory metal, the method comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2  (0<x<1), (Zr y , Ti 1-y )O 2  (0<y<1), (Hf z , Ti 1-z )O 2  (0<z<1), (Zr k , Ti l , Hf m )O 2  (0<k, l, m<1, k+l+m=1), and, forming an upper electrode of said capacitor on said capacitor dielectric film, so that the capacitor is constituted of said lower electrode, said capacitor dielectric film and said upper electrode.  
   
   
       17 . A method claimed in  claim 16  wherein after formation of said capacitor dielectric film, a heat treatment is carried out at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of said silicide of refractory metal occurs in said gate electrode and said source/drain diffused layers.  
   
   
       18 . A method claimed in  claim 16  wherein after formation of said upper electrode, a heat treatment is carried out at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of said silicide of refractory metal occurs in said gate electrode and said source/drain diffused layers.  
   
   
       19 . A method claimed in  claim 16  wherein said capacitor constitutes a cell capacitor of each DRAM cell and wherein said lower electrode, said capacitor dielectric film and said upper electrode are continuously deposited in the same machine.  
   
   
       20 . A method claimed in  claim 16  wherein said cell capacitor of each DRAM cell is of a cylinder type, and wherein after the formation of said upper electrode, said lower electrode, said capacitor dielectric film and said upper electrode, which are positioned in an upper portion of the cylinder, are removed so that a cylinder type capacitor is formed, and said upper electrode charged into an inside of the cylinder is connected to a common interconnection.  
   
   
       21 . A method for fabricating a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure formed on an insulator film formed on an interconnection layer, the method comprising the steps of forming a lower electrode of the capacitor, forming on said lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2  (0<x<1), (Zr y , Ti 1-y )O 2  (0<y<1), (Hf z , Ti 1-z )O 2  (0<z<1), (Zr k , Ti l , Hf m )O 2  (0<k, l, m<1, k+l+m=1), and then, forming an upper electrode on said capacitor dielectric film.  
   
   
       22 . A method of fabricating a semiconductor device comprising forming source and drain regions of a transistor, forming a metal plug in contact with one of the source and drain regions of said transistor, forming a lower metal electrode of a capacitor in contact with said metal plug, forming a capacitor dielectric film on said lower metal electrode by atomic layer deposition (ALD), and forming an upper metal electrode on said capacitor dielectric film, said capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2  (0<x<1), (Zr y , Ti 1-y )O 2  (0<y<1), (Hf z , Ti 1-z )O 2  (0<z<1) and (Zr k , Ti l , Hf m )O 2  (0<k, l, m<1, k+l+m=1), and said capacitor dielectric film having a film thickness of 5 to 15 nm, 
 whereby said semiconductor device results in a better electrical connection between said capacitor and said transistor and in suppressing a change in leakage current between said lower metal electrode and said upper metal electrode of said capacitor against a change in temperature irrespective of a thinner dielectric film thickness.    
   
   
       23 . The method as claimed in  claim 22 , wherein said upper electrode is formed by atomic layer deposition (ALD).  
   
   
       24 . The method as claimed in  claim 23 , wherein said lower electrode is formed by atomic layer deposition (ALD).  
   
   
       25 . A method of fabricating a semiconductor device comprising forming first and second diffusion regions of a transistor selectively in a semiconductor substrate, forming first and second metal silicide layers on respective surface portions of said first and second diffusion regions, covering said semiconductor substrate and said transistor with a first insulating layer, forming first and second holes in said first insulating layer to expose respective parts of said first and second metal silicide layers, filling said first and second holes with first and second metal plugs respectively, forming a bit line formed over said first insulating layer in contract with said first metal plug, forming a second insulating layer formed over said first insulating layer and said bit line, forming a third contact hole in said second insulating layer, filling said third hole with a third metal plug, and forming a lower metal electrode of a capacitor in contact with said third metal plug, forming a dielectric film on said lower metal electrode by atomic layer deposition (ALD), said dielectric film being made of a dielectric material selected from the group consisting of ZrO 2 , HfO 2 , (Zr x , Hf 1-x )O 2  (0<x<1), (Zr y , Ti 1-y )O 2  (0<y<1), (Hf z , Ti 1-z )O 2  (0<z<1), and (Zr k , Ti l , Hf m )O 2  (0<k, l, m<1, k+l+m=1), and forming an upper metal electrode on said dielectric film, whereby said semiconductor device results in a better electrical connection between said capacitor and said transistor without aggregation of said first and second metal silicide layers occurring and in suppressing a change in leakage current between said lower metal electrode and said upper metal electrode of said capacitor against a change in temperature.  
   
   
       26 . The method as claimed in  claim 25 , wherein said upper electrode is formed by atomic layer deposition (ALD).  
   
   
       27 . The method as claimed in  claim 26 , wherein said lower electrode is formed by atomic layer deposition (ALD).