Low latency buffer control system and method

Abstract

A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffers coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

1 . A method, comprising: 
 monitoring a first bus for transactions;    enabling at least one buffer when a transaction is detected, the at least one buffer to drive a signal on a second bus;    determining whether the detected transaction is a memory transaction; and    disabling the at least one buffer if the transaction is not a memory transaction.    
   
   
       2 . The method of  claim 1 , further comprising decoding the detected transaction.  
   
   
       3 . The method of  claim 1 , further comprising storing the detected transaction in a storage element.  
   
   
       4 . The method of  claim 1 , terminating the second bus to a mid-range voltage.  
   
   
       5 . An apparatus, comprising: 
 means for monitoring a first bus for transactions;    a buffer to drive a signal on a targeted memory bus;    means for enabling the buffer when a transaction is detected;    means for determining whether the detected transaction is a transaction for a device coupled to the targeted memory bus; and    means for disabling the buffer if the detected transaction is determined not to be a transaction for a device coupled to the targeted memory bus.    
   
   
       6 . The apparatus of  claim 5 , further comprising means for receiving the transaction.  
   
   
       7 . The apparatus of  claim 6 , wherein the means for receiving includes a storage device.  
   
   
       8 . The apparatus of  claim 5 , wherein the second bus is terminated to a mid-range voltage.  
   
   
       9 . A method, comprising: 
 monitoring a transaction queue;    decoding a transaction in the transaction queue;    determining whether the decoded transaction is a memory transaction; and    disabling at least one buffer coupled to a memory bus if the transaction is not a memory transaction.    
   
   
       10 . The method of  claim 9 , further comprising presenting a high impedance to the memory bus when the buffer is disabled.  
   
   
       11 . The method of  claim 9 , further comprising terminating the memory bus to a mid-range voltage.  
   
   
       12 . A method, comprising: 
 monitoring a first bus to detect transactions;    storing detected transactions in a queue;    decoding a transaction being output by the queue;    determining whether the decoded transaction is targeted for a memory bus;    enabling at least one buffer if not already enabled if the decoded transaction is targeted for the memory bus, the at least one buffer being coupled to the memory bus; and    disabling the at least one buffer if the decoded transaction is not targeted for the memory bus.    
   
   
       13 . The method of  claim 12 , further comprising delaying performance of the decoded transaction until after enabling the at least one buffer.  
   
   
       14 . The method of  claim 13 , further comprising: 
 performing the decoded transaction; and    disabling the at least one buffer after performing the decoded transaction.    
   
   
       15 . A method, comprising: 
 monitoring a first bus to detect transactions;    storing detected transactions in a queue;    decoding a transaction being output by the queue;    determining whether the transaction is a memory transaction;    determining whether a plurality of buffers are enabled, wherein the plurality of buffers are coupled to a second bus;    enabling the plurality of buffers if the transaction is a memory transaction;    determining whether the transactions stored in queue are memory transactions; and    disabling the plurality of buffers if the transaction is not a memory transaction.    
   
   
       16 . The method of  claim 15 , further comprising disabling the plurality of buffers after performing the memory transaction.  
   
   
       17 . The method of  claim 16 , further comprising the plurality of buffers presenting a high impedance to the memory bus.  
   
   
       18 . The method of  claim 17 , further comprising terminating the memory bus to a mid-range voltage.  
   
   
       19 . The method of  claim 16 , further comprising decoding the memory transaction.  
   
   
       20 . The method of  claim 19 , further comprising enabling the plurality of buffers while the memory transaction is being decoded.  
   
   
       21 . A system comprising: 
 a processor;    a synchronous dynamic random access memory (SDRAM);    a memory controller coupled to the processor and to the SDRAM, wherein the memory controller includes: 
 a plurality of buffers coupled to a terminated memory bus;  
 a decoder to decode a transaction sent by the processor; and  
 a buffer control circuit, coupled to the decoder and the plurality of buffers, to detect the transaction and, in response thereto, to enable the plurality of buffers before the decoder completes decoding the transaction, wherein the buffer control circuit is configurable to determine whether the transaction is a memory transaction and to disable the plurality of buffers if the transaction is not a memory transaction.  
   
   
   
       22 . The system of  claim 21 , wherein the memory controller further comprises a transaction store coupled to the decoder.  
   
   
       23 . The system of  claim 22 , wherein the transaction store comprises a queue.  
   
   
       24 . A system comprising: 
 a processor;    a synchronous dynamic random access memory (SDRAM);    a memory controller coupled to the processor and the SDRAM, wherein the memory controller includes: 
 a plurality of buffers coupled to a memory bus, the memory bus being terminated to a mid-range voltage;  
 a transaction store to store transactions sent by the processor;  
 a decoder coupled to the transaction store to decode a transaction being output by the transaction store; and  
 a buffer control circuit coupled to the transaction store and the plurality of buffers, wherein the buffer control circuit is configurable to disable the plurality of buffers after the transaction is performed if the transaction store does not contain other transactions targeted for the terminated memory bus,  
 wherein the buffer control circuit is further configurable to determine whether a decoded transaction from the transaction store is targeted for the memory bus and in response thereto enable the plurality of buffers if they are not already enabled.  
   
   
   
       25 . The system of  claim 24 , wherein the buffer control circuit is further configurable to allow the plurality of buffers to remain enabled after the transaction is performed if the transaction store does contain a transaction targeted for the memory bus.  
   
   
       26 . The system of  claim 24 , wherein the transaction store comprises a queue.  
   
   
       27 . The system of  claim 24 , wherein the buffer control circuit is further configurable to delay performance of the decoded transaction after enabling the plurality of buffers.