US2005127409A1PendingUtilityA1

System for high-precision double-diffused MOS transistors

43
Priority: Dec 28, 2001Filed: Jan 25, 2005Published: Jun 16, 2005
Est. expiryDec 28, 2021(expired)· nominal 20-yr term from priority
H10D 64/519H10D 62/393H10D 30/64H10D 62/127
43
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Claims

Abstract

The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region ( 404, 516, 616 ), and an oxide region ( 414, 512, 608 ) overlapping the moat region. A double-diffusion region ( 402, 504, 618 ) is formed within the oxide region, having end cap regions ( 406, 502, 620 ) that are effectively deactivated utilizing geometric and implant manipulations.

Claims

exact text as granted — not AI-modified
1 - 11 . (canceled)  
   
   
       12 . A double diffused semiconductor device comprising: 
 a moat region;    an oxide region overlappingly disposed over the moat region; and    a double-diffusion region, disposed within the oxide region, having end cap regions thereto that are effectively deactivated.    
   
   
       13 . The device of  claim 12 , wherein the end cap regions are disposed within the oxide region but outside the moat region.  
   
   
       14 . The device of  claim 12 , wherein the end cap regions are disposed within the oxide and moat regions.  
   
   
       15 . The device of  claim 13 , wherein a portion of the double-diffusion within the moat region is formed having substantially straight edges.  
   
   
       16 . The device of  claim 13 , wherein a portion of the double-diffusion within the moat region is formed having concave edges flaring out towards the end cap regions.  
   
   
       17 . The device of  claim 14 , wherein the double diffusion region is formed having minimal width and minimal length end cap regions.  
   
   
       18 . The device of  claim 14 , wherein the end cap regions are implanted with an opposite type material.  
   
   
       19 . The device of  claim 18 , wherein the double diffusion region comprises an n-type material and a p-type material is implanted in the end cap regions.  
   
   
       20 . A double diffused MOS transistor comprising: 
 a moat region;    an oxide region laterally and overlappingly disposed over the moat region;    a double-diffusion region, having semi-spherical end cap regions at opposite ends, disposed within the oxide and moat regions;    a source contact formed within the double diffusion region;    a drain contact formed within the moat region outside the double diffusion region; and    opposite type implants disposed within the end cap regions.

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