Method and apparatus of stress relief in semiconductor structures

Abstract

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

1 . A semiconductor integrated circuit device, comprising: 
 a plurality of electrically conductive vias for electrically connecting metal layers of said device;    a first dielectric layer overlying said vias; and    a stress relief layer, said stress relief layer overlying said vias and interposed between said vias and said first dielectric layer.    
   
   
       2 . The device of  claim 1 , wherein said first dielectric layer comprises a layer of a first dielectric material, the device further comprising a layer of a second dielectric material overlying said layer of first dielectric material.  
   
   
       3 . The device of  claim 2 , wherein said first dielectric material comprises an oxide material and said second dielectric material comprises a nitride material.  
   
   
       4 . The device of  claim 1 , further comprising a second dielectric layer overlying said vias and interposed between said vias and said stress relief layer.  
   
   
       5 . The device of  claim 4 , wherein the second dielectric layer comprises a cap layer.  
   
   
       6 . The device of  claim 4 , wherein the second dielectric layer comprises a nitride layer.  
   
   
       7 . The device of  claim 4 , wherein the second dielectric layer is less flexible than the stress relief layer.  
   
   
       8 . The device of  claim 1 , wherein the first dielectric layer is less flexible than the stress relief layer.  
   
   
       9 . The device of  claim 1 , wherein said stress relief layer comprises a low-k material.  
   
   
       10 . The device of  claim 9 , wherein said stress relief layer comprises a polymer thermoset resin.  
   
   
       11 . The device of  claim 1 , wherein said first dielectric layer comprises an oxide layer.  
   
   
       12 . The device of  claim 1 , wherein the first dielectric layer comprises a nitride layer.  
   
   
       13 . The device of  claim 1 , wherein said stress relief layer has a thickness of about 1000 Å.  
   
   
       14 . The device of  claim 1 , wherein the vias are embedded within a further dielectric layer that underlies said stress relief layer, wherein said further dielectric layer comprises a low-k dielectric material.  
   
   
       15 . The device of  claim 14 , wherein the further dielectric layer comprises a material that is more flexible than the first dielectric layer.  
   
   
       16 . The device of  claim 1 , further comprising a cap layer overlying said stress relief layer and interposed between said stress relief layer and said first dielectric layer.  
   
   
       17 . The device of  claim 16 , wherein said first dielectric layer comprises a layer of a first dielectric material, the device further comprising a layer of a second dielectric material overlying said layer of first dielectric material.  
   
   
       18 . The device of  claim 17 , wherein said first dielectric material comprises an oxide material and said second dielectric material comprises a nitride material.  
   
   
       19 . A method of making a semiconductor integrated circuit, the method comprising: 
 forming a first dielectric layer;    forming a recess in the first dielectric layer;    forming a conductor within the recess;    forming a stress relief layer over the first dielectric layer and the conductor; and    forming a second dielectric layer over the stress relief layer.    
   
   
       20 . The method of  claim 19 , further comprising forming a third dielectric layer over the second dielectric layer, the third dielectric layer being formed of a different material than the second dielectric layer.  
   
   
       21 . The method of  claim 19 , wherein the stress relief layer comprises a low-k dielectric material.  
   
   
       22 . The method of  claim 21 , wherein the stress relief layer comprises a thermoset polymer resin.  
   
   
       23 . The method of  claim 19 , further comprising forming a third dielectric layer over the first dielectric layer, wherein forming a stress relief layer comprises forming a stress relief layer over the third dielectric layer.  
   
   
       24 . The method of  claim 23 , wherein the third dielectric layer comprises a cap layer.