Semiconductor device

Abstract

A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.

1 . A semiconductor device having a plurality of semiconductor chips, comprising: 
 a first semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof;    a second semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof, the second semiconductor chip being disposed side by side laterally of the first semiconductor chip and thinner than the first semiconductor chip in thickness;    a first chip mounting section connected to the first semiconductor chip;    a second chip mounting section connected to the second semiconductor chip;    a plurality of leads disposed around the first and second semiconductor chips;    a plurality of conductive first wires which electrically connect the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip respectively;    a plurality of conductive second wires which electrically connect the electrodes of the first semiconductor chip and the leads respectively, the second wires being disposed so as to jump over the second semiconductor chip and formed with loops at positions higher than loops of the first wires; and    an encapsulating body which resin-seals the first and second semiconductor chips, and the plurality of first and second wires.    
     
     
         2 . A semiconductor device according to  claim 1 , wherein part of a back surface of the first semiconductor chip is adhered to part of the encapsulating body.  
     
     
         3 . A semiconductor device according to  claim 2 , wherein part of a back surface of the second semiconductor chip is adhered to part of the encapsulating body.  
     
     
         4 . A semiconductor device according to  claim 1 , wherein a slit is formed in an area between the first chip mounting section and the second chip mounting section of a chip mounting section in which the first chip mounting section and the second chip mounting section are integrally formed, and part of the encapsulating body is embedded into the slit.  
     
     
         5 . A semiconductor device according to  claim 1 , wherein the chip mounting section in which the first chip mounting section and the second chip mounting section are integrally formed, is formed point-symmetrically with respect to the center in a plane direction, of the semiconductor device.  
     
     
         6 . A semiconductor device according to  claim 1 , wherein the first semiconductor chip has a computation processing function and the second semiconductor chip has a memory circuit.  
     
     
         7 . A semiconductor device according to  claim 1 , wherein the first semiconductor chip is provided with a test circuit which tests a memory circuit provided outside the first semiconductor chip.  
     
     
         8 . A semiconductor device having a plurality of semiconductor chips, comprising: 
 a first semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof;    a second semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof and disposed side by side laterally of the first semiconductor chip;    a first chip mounting section connected to the first semiconductor chip;    a second chip mounting section connected to the second semiconductor chip and formed thinner than the first chip mounting section;    a plurality of leads disposed around the first and second semiconductor chips;    a plurality of conductive first wires which electrically connect the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip respectively;    a plurality of conductive second wires which electrically connect the electrodes of the first semiconductor chip and the leads respectively, the second wires being disposed so as to jump over the second semiconductor chip and formed with loops at positions higher than loops of the first wires; and    an encapsulating body which resin-seals the first and second semiconductor chips, and the plurality of first and second wires.    
     
     
         9 . A semiconductor device according to  claim 8 , wherein a slit is formed in an area between the first chip mounting section and the second chip mounting section of a chip mounting section in which the first chip mounting section and the second chip mounting section are integrally formed, and part of the encapsulating body is embedded into the slit.  
     
     
         10 . A semiconductor device according to  claim 8 , wherein the chip mounting section in which the first chip mounting section and the second chip mounting section are integrally formed, is formed point-symmetrically with respect to the center in a plane direction, of the semiconductor device.  
     
     
         11 . A semiconductor device having a plurality of semiconductor chips, comprising: 
 a first semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof;    a second semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof and disposed side by side laterally of the first semiconductor chip;    a first chip mounting section disposed below the plurality of electrodes of the first semiconductor chip in association with the plurality of electrodes thereof and connected to the first semiconductor chip;    a second chip mounting section disposed below the plurality of electrodes of the second semiconductor chip in association with the plurality of electrodes thereof and connected to the second semiconductor chip;    a plurality of leads disposed around the first and second semiconductor chips;    a plurality of conductive first wires which electrically connect the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip respectively;    a plurality of conductive second wires which electrically connect the electrodes of the first semiconductor chip and the leads respectively; and    an encapsulating body which resin-seals the first and second semiconductor chips, and the plurality of first and second wires,    wherein part of a back surface of the first semiconductor chip and part of a back surface of the second semiconductor chip are respectively adhered to part of the encapsulating body.    
     
     
         12 . A semiconductor device according to  claim 11 , wherein a slit is formed in an area between the first chip mounting section and the second chip mounting section of a chip mounting section in which the first chip mounting section and the second chip mounting section are integrally formed, and part of the encapsulating body is embedded into the slit.  
     
     
         13 . A semiconductor device according to  claim 11 , further comprising a plurality of outer leads formed integrally with inner leads corresponding to the leads, wherein the plurality of outer leads respectively protrude from the four sides of the encapsulating body and formed with being bent in gull-wing form.  
     
     
         14 . A semiconductor device having a plurality of semiconductor chips, comprising: 
 a first semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof;    a second semiconductor chip having a semiconductor element and a plurality of electrodes over a main surface thereof, the second semiconductor chip being disposed side by side laterally of the first semiconductor chip and having a plane shape formed in rectangular form;    a first chip mounting section connected to the first semiconductor chip;    a second chip mounting section connected to the second semiconductor chip;    a plurality of leads disposed around the first and second semiconductor chips;    a plurality of conductive first wires which electrically connect the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip respectively;    a plurality of conductive second wires which electrically connect the electrodes of the first semiconductor chip and the leads respectively; and    an encapsulating body which resin-seals the first and second semiconductor chips, and the plurality of first and second wires,    wherein a relationship between a distance P in a direction parallel to the direction of a short side of the second semiconductor chip between a center in a plane direction, of the first semiconductor chip and a center in a plane direction, of the semiconductor device, and a length C of the short side of the second semiconductor chip is given as P<(C/2).    
     
     
         15 . A semiconductor device according to  claim 14 , wherein the first semiconductor chip has a plane shape formed in rectangular form, and a long side of the first semiconductor chip and a long side of the second semiconductor chip are disposed opposite to each other.  
     
     
         16 . A semiconductor device according to  claim 14 , wherein the plurality of second wires connected to the first semiconductor chip are disposed in plural form with respect to the four directions corresponding to the four sides of the encapsulating body.  
     
     
         17 - 20 . (canceled)