Bump structure for a semiconductor device and method of manufacture

Abstract

A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.

1 . A semiconductor device, comprising: 
 a plurality of bump structures arrayed along a substrate in a first direction, each bump structure having a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure having a sidewall facing in the first direction that is non-conductive.    
   
   
       2 . The semiconductor device of  claim 1 , wherein each bump structure has at least one non-conductive sidewall facing in the first direction.  
   
   
       3 . The semiconductor device of  claim 2 , wherein each bump structure has two oppositely facing non-conductive sidewalls facing in the first direction.  
   
   
       4 . The semiconductor device of  claim 3 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.  
   
   
       5 . The semiconductor device of  claim 4 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.  
   
   
       6 . The semiconductor device of  claim 4 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.  
   
   
       7 . The semiconductor device of  claim 4 , wherein successively arrayed bump structures are disposed offset from one another in the second direction along the substrate.  
   
   
       8 . The semiconductor device of  claim 7 , wherein the second direction is substantially perpendicular to the first direction.  
   
   
       9 . The semiconductor device of  claim 2 , wherein each bump structure has one non-conductive sidewall facing in the first direction and one conductive sidewall facing in the first direction such that the conductive sidewall does not face the conductive sidewall of another bump structure.  
   
   
       10 . The semiconductor device of  claim 9 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.  
   
   
       11 . The semiconductor device of  claim 10 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.  
   
   
       12 . The semiconductor device of  claim 10 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.  
   
   
       13 . The semiconductor device of  claim 10 , wherein successively arrayed bump structures are disposed offset from one another in the second direction along the substrate.  
   
   
       14 . The semiconductor device of  claim 13 , wherein the second direction is substantially perpendicular to the first direction.  
   
   
       15 . The semiconductor device of  claim 1 , Wherein the array of bump structures alternate from a first type to a second type, the bump structure of the first type has two oppositely facing non-conductive sidewalls that face in the first direction, and the bump structure of the second type has each sidewall being conductive.  
   
   
       16 . The semiconductor device of  claim 15 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.  
   
   
       17 . The semiconductor device of  claim 16 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.  
   
   
       18 . The semiconductor device of  claim 16 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.  
   
   
       19 . The semiconductor device of  claim 16 , wherein successively arrayed bump structures are disposed offset from one another in the second direction along the substrate.  
   
   
       20 . The semiconductor device of  claim 19 , wherein the second direction is substantially perpendicular to the first direction.  
   
   
       21 . The semiconductor device of  claim 1 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.  
   
   
       22 . The semiconductor device of  claim 21 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.  
   
   
       23 . The semiconductor device of  claim 21 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.  
   
   
       24 . The semiconductor device of  claim 23 , wherein the lower metal layer has a thickness of 0.05 to 1 um, and the upper metal layer has a thickness of 1 to 10 um.  
   
   
       25 . The semiconductor device of  claim 23 , wherein the lower metal layer includes at least one of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, and NiV/Cu, and the upper metal layer includes at least one of Au, Ni, Cu, Pd, Ag, and Pt.  
   
   
       26 . The semiconductor device of  claim 1 , wherein successively arrayed bump structures are disposed offset from one another in a second direction along the substrate.  
   
   
       27 . The semiconductor device of  claim 26 , wherein the second direction is substantially perpendicular to the first direction.  
   
   
       28 . The semiconductor device of  claim 1 , wherein the bump structures have a width of 10 to 50 um.  
   
   
       29 . The semiconductor device of  claim 1 , wherein each bump structure includes a non-conductive bump and a conductive material disposed on at least a top surface of the non-conductive bump.  
   
   
       30 . The semiconductor device of  claim 29 , wherein each bump has a height of 2-30 um.  
   
   
       31 . The semiconductor device of  claim 29 , wherein each bump structure includes the conductive material disposed on two oppositely facing sidewalls that face in the second direction, and the conductive material extends over the substrate from each of the two oppositely facing sidewalls.  
   
   
       32 . The semiconductor device of  claim 29 , wherein each bump includes one of a polyimide, benzo cyclo butane, poly benzoxazole, and photosensitive resin.  
   
   
       33 . A semiconductor device, comprising: 
 a plurality of bumps arrayed along a substrate in a first direction;    a plurality of conductive lines formed in a second direction, each conductive line associated with one of the bumps, each conductive line disposed over a top surface of the associated bump and disposed over two oppositely facing sidewalls of the bump that face in the second direction, and each conductive line extending over the substrate from each of the two oppositely facing sidewalls.    
   
   
       34 . A semiconductor device, comprising: 
 a plurality of bumps arrayed along a substrate in a first direction, each bump having a width in the first direction greater than a pitch gap between successively arrayed bumps; and    a plurality of conductive lines formed in a second direction, each conductive line associated with one of the bumps, each conductive line disposed over a top surface of the associated bump and disposed over a sidewall of the associated bump that faces in the second direction, and each conductive line extending over the substrate from the sidewall facing in the second direction.    
   
   
       35 . A method of forming a semiconductor device, comprising: 
 forming a plurality of bump structures arrayed along a substrate in a first direction, each bump structure having a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure having a sidewall facing in the first direction that is non-conductive.    
   
   
       36 . The method of  claim 35 , wherein the forming step comprises: 
 forming a plurality of bumps arrayed along the substrate in the first direction; and    forming a conductive line associated with each bump in a second direction, each conductive line disposed over a top surface of the associated bump and disposed over a sidewall of the associated bump that faces in the second direction, and each conductive line extending over the substrate from the sidewall facing in the second direction.    
   
   
       37 . The method of  claim 35 , wherein the forming a plurality of bumps step comprises: 
 spin coating a bump material on the substrate; and    patterning the bump material to form the plurality of bumps.    
   
   
       38 . The method of  claim 37 , wherein each bump includes one of a polyimide, benzo cyclo butane, poly benzoxazole, and photosensitive resin.  
   
   
       39 . The method of  claim 37 , wherein the patterning step forms the plurality of bumps such that each bump has a width of 10 to 50 um.  
   
   
       40 . The method of  claim 37 , wherein the patterning step forms the plurality of bumps such that each bump has a height of 2-30 um.  
   
   
       41 . The method of  claim 35 , wherein each conductive line includes at least a lower metal layer and an upper metal layer.  
   
   
       42 . The method of  claim 41 , wherein the lower metal layer has a thickness of 0.05 to 1 um, and the upper metal layer has a thickness of 1 to 10 um.  
   
   
       43 . The method of  claim 41 , wherein the lower metal layer includes at least one of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, and NiV/Cu, and the upper metal layer includes at least one of Au, Ni, Cu, Pd, Ag, and Pt.  
   
   
       44 . The method of  claim 41 , wherein the forming a conductive line step comprises: 
 forming the lower metal layer; and    electroplating the lower metal layer with an upper metal layer material to form the upper metal layer.    
   
   
       45 . The semiconductor device of  claim 35 , wherein each bump structure has at least one non-conductive sidewall facing in the first direction.  
   
   
       46 . The semiconductor device of  claim 35 , wherein each bump structure has two oppositely facing non-conductive sidewalls facing in the first direction.  
   
   
       47 . The semiconductor device of  claim 35 , wherein each bump structure has one non-conductive sidewall facing in the first direction and one conductive sidewall facing in the first direction such that the conductive sidewall does not face the conductive sidewall of another bump structure.  
   
   
       48 . The semiconductor device of  claim 35 , wherein the array of bump structures alternate from a first type to a second type, the bump structure of the first type has two oppositely facing non-conductive sidewalls that face in the first direction, and the bump structure of the second type has each sidewall being conductive.  
   
   
       49 . A method of forming a semiconductor device, comprising: 
 forming a plurality of bumps arrayed along a substrate in a first direction, each bump having a width in the first direction greater than a pitch gap between successively arrayed bumps; and    forming a plurality of conductive lines formed in a second direction, each conductive line associated with one of the bumps, each conductive line disposed over a top surface of the associated bump and disposed over a sidewall of the associated bump that faces in the second direction, and each conductive line extending over the substrate from the sidewall facing in the second direction.