Semiconductor device with source line and fabrication method thereof

Abstract

A semiconductor device comprises a plurality of field-effect transistors and a common source line. Each of the plurality of memory cell transistors includes a semiconductor region of a first conductivity type formed in a semiconductor substrate, a source region and a drain region of a second conductivity type formed in the semiconductor region, an information storage portion capable of electrically writing and erasing data, and at least one control gate electrode including a conductive layer. The common source line is formed on the semiconductor region of the first conductivity type, and electrically connects the source regions of the memory cell transistors. The common source line includes a conductive layer that has a film thickness substantially equal to a film thickness of the conductive layer included in the control gate electrode and is formed of the same material as that of the conductive layer included in the control gate electrode.

1 - 37 . (canceled)  
   
   
       38 . A semiconductor device comprising: 
 a plurality of memory cell transistors, each of the plurality of memory cell transistors including: 
 a semiconductor region of a first conductivity type formed in a semiconductor substrate,  
 a source region and a drain region of a second conductivity type formed in the semiconductor region of the first conductivity type,  
 a gate insulation film formed on the semiconductor region between the source region and the drain region, the gate insulation film including a first insulation film, an information storage layer on the first insulation film and a second insulation film on the information storage layer, and  
 at least one control gate electrode formed on the gate insulation film, the control gate electrode including a conductive layer; and  
   a common source line electrically connected a plurality of the source regions of the plurality of memory cell transistors, and the common source line including a conductive layer that has a film thickness substantially equal to a film thickness of the conductive layer included in the control gate electrode and is formed of the same material as that of the conductive layer included in the control gate electrode.    
   
   
       39 . A semiconductor device comprising: 
 a plurality of memory cell transistors, each of the plurality of memory cell transistors including: 
 a semiconductor region of a first conductivity type formed in a semiconductor substrate,  
 a source region and a drain region of a second conductivity type formed in the semiconductor region of the first conductivity type,  
 a gate insulation film formed on the semiconductor region between the source region and the drain region, the gate insulation film including a first insulation film, an information storage layer on the first insulation film and a second insulation film on the information storage layer, and  
 at least one control gate electrode formed on the gate insulation film, the control gate electrode including: 
 a conductive layer;  
 a plurality of select transistors, each of the plurality of select transistors including: 
 a source region and a drain region of the second conductivity type formed in the semiconductor region of the first conductivity type, and  
 at least one control gate electrode including a conductive layer; and  
 
 
   a common source line electrically connected a plurality of the source regions of the plurality of select transistors, and the common source line including a conductive layer that has a film thickness substantially equal to a film thickness of the conductive layer included in the control gate electrode of at least one of the memory cell transistor and the select transistor, and the conductive layer included in the common source line being formed of the same material as that of the conductive layer included in the control gate electrode of the at least one of the memory cell transistor and the select transistor.    
   
   
       40 . A semiconductor device comprising: 
 a memory cell transistor including a first gate insulation film and a first control gate, the first control gate being formed on a semiconductor substrate with the first gate insulation film interposed between the semiconductor substrate and the first control gate, the first control gate including a conductive film, and the first gate insulation film including a stacked structure wherein a tunnel insulation film, a charge accumulation layer and a block insulation film are successively stacked on the semiconductor substrate;    a select transistor including a second gate insulation film and a second control gate, the second control gate being formed on the semiconductor substrate with the second gate insulation film interposed between the semiconductor substrate and the second control gate, and the second control gate being formed of the same material as that of the first control gate; and    a source line formed on the semiconductor substrate, the source line including a conductive film formed of the same material as that of the first control gate.    
   
   
       41 . The semiconductor device according to  claim 40 , wherein the second gate insulation film is formed of the same material as that of the first gate insulation film, and is the same continuous film as the first gate insulation film.  
   
   
       42 . The semiconductor device according to  claim 40 , wherein each of the first control gate, the second control gate and the conductive film includes a polysilicon film and one selected from the group consisting of a silicide film, a silicon-metal compound and a metal film, which is formed on the polysilicon film.  
   
   
       43 . The semiconductor device according to  claim 40 , wherein each of the first control gate, the second control gate and the conductive film includes one of a silicon-metal compound and a metal film.  
   
   
       44 . The semiconductor device according to  claim 40 , wherein a height from a surface of the semiconductor substrate to an upper surface of the conductive film of the source line is lower than a height from the surface of the semiconductor substrate to an upper surface of the first control gate of the memory cell transistor.