Modified source/drain re-oxidation method and system

Abstract

Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self align source resistance.

1 . A method of memory cells comprising: 
 defining a dimension of a flash cell on a substrate utilizing photolithography and plasma etching to provide steep walls in the substrate;    fabricating a drain in a drain region of the substrate by: 
 blocking a source region of the flash cell;  
 implanting arsenic; and  
 removing blocking from the source region;  
   fabricating a self aligned source in the source region of the substrate by: 
 blocking the drain region of the flash cell;  
 performing an oxide dry etch in order to remove isolation oxide along the self aligned source region;  
 implanting phosphorous to dope the self aligned source;  
 implanting arsenic to dope the self aligned source; and  
 removing blocking from the drain region of the flash cell;  
   selecting at least an erase rate by a desired thickness and a desired phosphorous concentration of a phosphorous doped oxide layer;    using chemical vapor deposition to provide the phosphorous doped oxide layer having the desired thickness and the desired phosphorous concentration over and in places, in contact with the substrate;    performing a directional plasma etch on the phosphorous doped oxide layer to form sidewalls in contact with both the substrate and the steep walls; and    performing re-oxidation on the substrate to form a desired oxide profile width in the self aligned source region adjacent the steep walls which is less than a width of an oxide profile that can be provided in the absence of the phosphorous doped oxide sidewalls.    
   
   
       2 . A method of fabricating memory cells comprising: 
 doping a drain region in a substrate with a first dopant;    doping a source region in the substrate with a second dopant;    depositing a doped oxide layer over the substrate according to a desired thickness and a desired phosphorus concentration used to provide at least a desired erasure rate;    selectively removing horizontal portions of the doped oxide layer while leaving steep portions along steep exposed side-walls; and    performing re-oxidization on the substrate to provide a desired oxide profile width which is less than an oxide profile width that can be provided in the absence of the doped oxide layer.    
   
   
       3 . The method of  claim 2 , wherein a thickness of the doped oxide layer is in the range of 25 Å to 500 Å.  
   
   
       4 . The method of  claim 2 , wherein said phosphorous concentration is in the range of about 1% to about 6%.  
   
   
       5 . A method of fabricating memory cells comprising: 
 providing a substrate having a memory cell;    doping one or more horizontal surfaces of said memory cell to a first dopant concentration;    doping one or more vertical surfaces of said memory cell coupled to said one or more horizontal surfaces to a second dopant concentration, said second dopant concentration being lower than said first dopant concentration; and    forming one or more phosphorous doped oxide sidewalls horizontally in contact with said substrate and vertically in contact with said one or more vertical surfaces of said memory cell, said one or more vertical phosphorous doped oxide sidewalls having an additional dopant concentration.    
   
   
       6 . The method of  claim 5 , wherein said additional dopant concentration and said second dopant concentration produce an effective dopant concentration.  
   
   
       7 . The method of  claim 5 , wherein said effective dopant concentration is substantially equal to the first dopant concentration.  
   
   
       8 . The method of  claim 5 , wherein the additional dopant concentration, the second dopant concentration, and the first dopant concentration are selected to provide a desired resistance.  
   
   
       9 . The method of  claim 5  further comprising subjecting said substrate to re-oxidation.  
   
   
       10 . The method of  claim 5  further comprising etching said substrate.  
   
   
       11 . The method of  claim 5 , wherein said doping is prior to said re-oxidation.  
   
   
       12 . The method of  claim 5 , wherein said re-oxidation increases doping in said one or more vertical surfaces from phosphorus diffusing out of said one or more phosphorous doped oxide sidewalls.  
   
   
       13 . The method of  claim 5 , wherein said re-oxidation forms a re-oxidation oxide layer over said one or more phosphorous doped oxide sidewalls and said one or more horizontal surfaces.  
   
   
       14 . The method of  claim 5 , wherein said re-oxidation is accomplished by thermal re-oxidation.  
   
   
       15 . The method of  claim 5 , wherein said sidewalls is formed by providing a phosphorous doped oxide layer having a thickness in the range of about 25 Å to about 500 Å, and etching said phosphorous doped oxide layer.  
   
   
       16 . The method of  claim 5 , wherein said additional dopant concentration is a phosphorous concentration from about 1% to about 6%.  
   
   
       17 . A method of fabricating memory cells comprising: 
 providing a substrate;    forming a self align source having one or more horizontal surfaces substantially planar to the substrate with a first dopant concentration, one or more vertical surfaces substantially perpendicular and coupled to the one or more horizontal surfaces with a second dopant concentration, said second dopant concentration being lower than said first dopant concentration, and a first one or more substantially vertical phosphorous doped oxide layers formed over the one or more vertical surfaces;    forming a tunnel oxide layer over at least a portion of the self aligned source;    forming a floating gate layer over at least a portion of said tunnel oxide layer;    forming a dielectric layer over at least a portion of said floating gate layer;    forming a wordline poly layer over at least a portion of said dielectric layer;    forming a fielding isolation oxide layer over at least a portion of said wordline poly layer;    patterning one or more of the formed layers to from substantially vertical surfaces; and    forming a second one or more substantially vertical phosphorous doped oxide layers vertically in contact with said substantially vertical surfaces and horizontally in contact with said substrate, said first and second one or more substantially vertical phosphorous doped oxide layers having an additional dopant concentration.    
   
   
       18 . The method of  claim 17 , wherein said substantially vertical phosphorous doped oxide layers have a thickness in the range of about 25 Å to about 500 Å.  
   
   
       19 . The method of  claim 17 , wherein said additional dopant concentration is a phosphorous concentration from about 1% to about 6%.  
   
   
       20 . The method of  claim 17 , wherein said additional dopant concentration and said second dopant concentration produce an effective dopant concentration.  
   
   
       21 . The method of  claim 17 , wherein said effective dopant concentration is substantially equal to the first dopant concentration.  
   
   
       22 . The method of  claim 17 , wherein the additional dopant concentration, the second dopant concentration, and the first dopant concentration are selected to provide a desired resistance.  
   
   
       23 . The method of  claim 17  further comprising subjecting said substrate to re-oxidation.  
   
   
       24 . The method of  claim 17  further comprising etching said substrate.  
   
   
       25 . The method of  claim 17  further comprising utilizing shallow trench isolation.  
   
   
       26 . The method of  claim 17 , wherein the floating gate layer is a lightly doped polysilicon layer.  
   
   
       27 . The method of  claim 17 , wherein the dielectric layer is an oxide-nitride-oxide.  
   
   
       28 . The method of  claim 17 , wherein the wordline layer is a polysilicon with a metal silicide.  
   
   
       29 . The method of  claim 17 , wherein said substrate is selected from silicon, gallium arsenide, germanium, and combination thereof.  
   
   
       30 . The method of  claim 17  further comprising performing a source/drain anneal.  
   
   
       31 . The method of  claim 17 , wherein forming includes depositing, doping, and patterning one or more said formed layers, wherein individually said first, second, and additional dopant concentrations is for a material selected from arsenic, boron, phosphor, an element from Group III and V of the periodic table, and combinations thereof.  
   
   
       32 . The method of  claim 17 , wherein said depositing is by chemical vapor deposition or spin on glass.