Stacked via-stud with improved reliability in copper metallurgy

Abstract

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

1 - 8 . (canceled)  
   
   
       9 . A method of forming a multilayer semiconductor integrated circuit structure comprising the steps of: 
 a) forming a first layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath;    b) forming multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and,    c) forming a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure comprising a cantilever formed in said low-k dielectric material.    
   
   
       10 . The method as claimed in  claim 9 , wherein a dielectric layer of each said multiple interconnect layers includes a soft low-k dielectric material, said cantilever being integrated within said soft low-k dielectric material at a level to increase resistance to thermal fatigue crack formation.  
   
   
       11 . The method as claimed in  claim 10 , wherein said soft low-k dielectric material includes SiLK, Aerogels, fluoridized polyimide, polymeric compound or air.  
   
   
       12 . The method as claimed in  claim 9 , wherein said cantilever structures are interwoven by connecting a cantilever on one level of interconnection to a bulk portion of a semiconductor line on an adjacent level of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.  
   
   
       13 . A multilevel semiconductor integrated circuit (IC) structure comprising: 
 a semiconductor substrate layer having formed therein a metal feature,    a first interconnect layer including low-k dielectric material formed over said substrate;    a first via stud in said first interconnect dielectric layer connecting said metal feature formed in said semiconductor substrate to a first metal interconnection line segment formed in said first dielectric layer;    a second interconnect layer including low-k dielectric material formed over said first interconnect dielectric layer;    a second via stud in said second interconnect dielectric layer aligned with and connecting said first metal interconnection line segment with a second metal interconnection line segment formed in said second dielectric layer, said second metal interconnection line segment of rectangular shape and at a selected location such that one end of the second metal line segment is above the first metal line segment of the same length and the width;    a third interconnect layer including low-k dielectric material formed over said second interconnect dielectric layer; and,    a third via stud in said third interconnect dielectric layer connecting said second metal interconnection line segment of rectangular shape at an opposite end thereof with a third metal interconnection line segment formed in said third dielectric layer,    said first, second and third integrated via-studs and said second metal line segment forming a stacked via-stud arrangement with said second metal line segment comprising a cantilever structure.    
   
   
       14 . The multilevel IC structure as claimed in  claim 9 , wherein a dielectric material of each said first, second and third interconnection dielectric layers includes a soft low-k dielectric material, said cantilever being integrated within said soft low-k dielectric material at a level to increase resistance to thermal fatigue crack formation.  
   
   
       15 . The multilevel IC structure as claimed in  claim 13 , further including a fourth interconnection dielectric level including low-k dielectric material above said third interconnection level and a fourth level integrated via-stud connecting said third metal line segment with a fourth metal interconnection line segment formed in said fourth dielectric layer, said third metal line segment comprising a second cantilever structure formed in said low-k dielectric material of said third dielectric layer.  
   
   
       16 . A multilevel semiconductor integrated circuit (IC) structure including: 
 a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath;    multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and,    a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure comprising a cantilever formed in said low-k dielectric material.    
   
   
       17 . The multilevel IC structure as claimed in  claim 16 , wherein said cantilever comprises a high conductivity metal, said cantilever disposed between two stacks of via-studs from said set of stacked via-studs.  
   
   
       18 . A redundant system for interconnecting conductive layers of a multiple layer semiconductor integrated circuit (IC), said redundant system comprising: 
 a plurality of interlaced metal via-studs for interconnecting a first conductive structure at a lower level interconnect structure lying over a substrate to a second conductive structure formed in an upper interconnect level, each said conductive structures lying in a layer of dielectric material;    a third conductive structure in an interconnect level between said lower and upper interconnect levels, said interconnect level including a low-k dielectric material, at least one of said metal via-studs connecting said first conductive structure to said third conductor structure at a bulkhead region end of said third conductive structure;    a gap being formed in said third conductive structure to result in one or more cantilever structures in said third conductive structure; and,    at least one of said metal via-studs connecting a free end of said cantilever structure a distance from said first metal via-stud to a bulkhead region formed in said second conductive structure at said upper level;    wherein said third conductive structure lies in a perpendicular fashion with respect to said upper and lower conductive structures to facilitate redundant paths connecting said first and second conductive layers via said third conductive layer.    
   
   
       19 . The redundant system as claimed in  claim 18 , wherein said second conductive layer includes a further cantilever structure, said cantilever structures of said second and third conductive structures being interwoven by connecting a cantilever on one conductive structure at a level of interconnection to a bulk portion of a conductive structure on an adjacent level of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.  
   
   
       20 . A flexible system for a multilevel interconnection including a bus line at one interconnection level, said system comprising: 
 a semiconductor substrate having metal features;    multiple layers of dielectric material over said substrate, each layer comprising at least a layer of a low strength low-k dielectric material;    a multilevel interconnection disposed within multilayers of dielectric, the multilevel interconnection comprising a flexible patterned structure;    the flexible patterned structure includes at least one cantilever structure formed by removing U-shaped metal formation within the width of a line, and at selected regions along a bus line;    a set of stacked via-studs formed substantially in said low strength low-k dielectric material for connecting the free end of the cantilever on one level of interconnection to the bulk of said bus line on another interconnection level.