Nitride-based transistors having laterally grown active region and methods of fabricating same

Abstract

High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.

1 . A high electron mobility transistor, comprising: 
 a first Group III-nitride layer having vertically grown regions, laterally grown regions between adjacent vertically grown regions and a coalescence region between adjacent laterally grown regions;    a Group III-nitride channel layer on the first Group III-nitride layer;    a Group III-nitride barrier layer on the Group III-nitride channel layer;    a drain contact on the barrier layer;    a source contact on the barrier layer;    a gate contact on the barrier layer; and    wherein the gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.    
   
   
       2 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a depletion region of a two-dimensional electron gas extends from the gate contact under expected operating conditions.  
   
   
       3 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a point where a strength of an electric field is 50% of a strength of an electric field at a drain side edge of the gate contact under expected operating conditions.  
   
   
       4 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a point where a strength of an electric field is an order of magnitude less than a strength of an electric field at a drain side edge of the gate contact under expected operating conditions.  
   
   
       5 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a point where a strength of an electric field is two orders of magnitude less than a strength of an electric field at a drain side edge of the gate contact under expected operating conditions.  
   
   
       6 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       7 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends to but not beyond the drain contact.  
   
   
       8 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is disposed extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the laterally grown region on which the gate contact is disposed.  
   
   
       9 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and wherein a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       10 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and wherein a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends to but not beyond the drain contact.  
   
   
       11 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and wherein a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the second laterally grown region.  
   
   
       12 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       13 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends to but not beyond the drain contact.  
   
   
       14 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the second laterally grown region.  
   
   
       15 . The transistor of  claim 1 , wherein the source contact is disposed on the barrier layer to extend across the coalescence region of the first Group III-nitride layer so as to bridge between two laterally grown regions of the first Group III-nitride layer.  
   
   
       16 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and wherein a portion of the source contact is disposed on a second laterally grown region adjacent the first laterally grown region.  
   
   
       17 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and wherein the source contact extends to but not beyond a second laterally grown region adjacent the first laterally grown region.  
   
   
       18 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and wherein the source contact does not extend to a second laterally grown region adjacent the first laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       19 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and wherein a portion of the source contact is disposed on the second laterally grown region.  
   
   
       20 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and wherein the source contact extends to but not beyond the second laterally grown region.  
   
   
       21 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and wherein the source contact does not extend to the second laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       22 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact and wherein a portion of the source contact is disposed on the first laterally grown region.  
   
   
       23 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact and wherein the source contact extends to but not beyond the first laterally grown region.  
   
   
       24 . The transistor of  claim 1 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact and wherein the source contact does not extend to the first laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       25 . The transistor of  claim 1 , wherein the first Group III-nitride layer is semi-insulating or insulating.  
   
   
       26 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is provided extends from beneath the source contact to beneath the drain contact.  
   
   
       27 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is provided extends from beneath the gate contact to beneath the drain contact.  
   
   
       28 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is provided extends from beneath the gate contact toward but not to beneath the drain contact.  
   
   
       29 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is provided extends from beneath the source contact toward but not to beneath the drain contact.  
   
   
       30 . The transistor of  claim 1 , wherein the laterally grown region on which the gate contact is provided extends a majority of the distance from source contact to the drain contact.  
   
   
       31 . The transistor of  claim 1 , further comprising a substrate, wherein the first Group III-nitride layer is provided on the substrate.  
   
   
       32 . The transistor of  claim 31 , wherein the substrate includes a trench and wherein the laterally grown regions extend over the trench.  
   
   
       33 . The transistor of  claim 32 , wherein the substrate comprises a silicon carbide substrate and wherein the trench extends perpendicular or parallel to a crystal plane of the silicon carbide substrate.  
   
   
       34 . The transistor of  claim 33 , wherein the crystal plane of the silicon carbide substrate is a plane in the {11{overscore (2)}0} family of planes or the {10{overscore (1)}0} family of planes.  
   
   
       35 . The transistor of  claim 32 , further comprising a mask layer in the trench.  
   
   
       36 . The transistor of  claim 31 , further comprising a mask pattern on the substrate and wherein the laterally grown regions extend over the mask pattern.  
   
   
       37 . The transistor of  claim 33 , wherein the laterally grown regions have substantially vertical growth sidewalls.  
   
   
       38 . The transistor of  claim 33 , wherein the laterally grown regions have trapezoidal growth sidewalls.  
   
   
       39 . The transistor of  claim 1 , wherein the first Group III-nitride layer comprises a gallium nitride layer having deep level impurities therein.  
   
   
       40 . The transistor of  claim 39 , wherein the deep level impurity comprises Fe.  
   
   
       41 . The transistor of  claim 1 , wherein the source contact, the gate contact and the drain contact each comprise a plurality of contact fingers and wherein the laterally grown regions comprise a plurality of laterally grown regions separated by vertically grown regions, where each gate contact finger is provided on a corresponding one of the plurality of laterally grown regions.  
   
   
       42 . The transistor of  claim 32 , wherein the trench comprises a plurality of trenches, the source contact, the gate contact and the drain contact each comprise a plurality of contact fingers and where each gate contact finger is disposed above a corresponding one of the plurality of trenches.  
   
   
       43 . A semiconductor device, comprising: 
 a silicon carbide die having a Group III-nitride layer thereon, the Group III-nitride layer having at least one vertically grown region and at least one laterally grown region;    at least one Group III-nitride transistor on the silicon carbide die; and    wherein the at least one laterally grown region does not extend substantially beyond a region of the silicon carbide die corresponding to the at least one Group III-nitride transistor.    
   
   
       44 . The semiconductor device of  claim 43 , wherein the at least one Group III-nitride transistor comprises a plurality of gate fingers and wherein the at least one laterally grown region comprises a plurality of laterally grown regions disposed beneath respective ones of the gate fingers of the at least on Group III-nitride transistor.  
   
   
       45 . The semiconductor device of  claim 43 , wherein the at least one Group III-nitride transistor comprises a plurality Group-III nitride transistors and wherein the at least one laterally grown region comprises a plurality of laterally grown regions corresponding to respective ones of the plurality of Group III-nitride transistors.  
   
   
       46 . The semiconductor device of  claim 43 , wherein the silicon carbide die comprises a portion of a silicon carbide wafer.  
   
   
       47 . The semiconductor device of  claim 46 , wherein the silicon carbide wafer includes a major flat and wherein the at least one laterally grown region has a boundary with a vertically grown region that is perpendicular or parallel to the major flat.  
   
   
       48 . The semiconductor device of  claim 43 , wherein the at least one Group III-nitride transistor comprises a gallium nitride-based high electron mobility transistor (HEMT).  
   
   
       49 . The semiconductor device of  claim 43 , further comprising at least one Group TIT-nitride transistor on the silicon carbide die in a region of the die other than the region of the die with the at least one laterally grown region.  
   
   
       50 . The semiconductor device of  claim 43 , further comprising at least one capacitor, resistor and/or inductor on the silicon carbide die in a region of the die other than the region of the die with the at least one laterally grown region.  
   
   
       52 . The semiconductor device of  claim 43 , wherein the at least one laterally grown region has a boundary with a vertically grown region that is aligned perpendicular or parallel to a crystal plane of the silicon carbide substrate.  
   
   
       53 . The semiconductor device of  claim 52 , wherein the crystal plane of the silicon carbide substrate is a plane in the {11{overscore (2)}0} family of planes or the {10{overscore (1)}0} family of planes.  
   
   
       54 . A method of fabricating a transistor, comprising: 
 forming a first Group III-nitride layer having vertically grown regions, laterally grown regions between adjacent vertically grown regions and a coalescence region between adjacent laterally grown regions;    forming a Group III-nitride channel layer on the first Group III-nitride layer;    forming a Group III-nitride barrier layer on the Group III-nitride channel layer;    forming a drain contact and a source contact on the barrier layer;    forming a gate contact on the barrier layer; and    wherein the gate contact is formed to be disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.    
   
   
       55 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a depletion region of a two-dimensional electron gas extends from the gate contact under expected operating conditions.  
   
   
       56 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a point where a strength of an electric field is 50% of a strength of an electric field at a drain side edge of the gate contact under expected operating conditions.  
   
   
       57 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a point where a strength of an electric field is an order of magnitude less than a strength of an electric field at a drain side edge of the gate contact under expected operating conditions.  
   
   
       58 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a point where a strength of an electric field is two orders of magnitude less than a strength of an electric field at a drain side edge of the gate contact under expected operating conditions.  
   
   
       59 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       60 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends to but not beyond the drain contact.  
   
   
       61 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is disposed extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the laterally grown region on which the gate contact is disposed.  
   
   
       62 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and wherein a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       63 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and wherein a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends to but not beyond the drain contact.  
   
   
       64 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and wherein a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the second laterally grown region.  
   
   
       65 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       66 . The method  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends to but not beyond the drain contact.  
   
   
       67 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the second laterally grown region.  
   
   
       68 . The method of  claim 54 , wherein the source contact is disposed on the barrier layer to extend across the coalescence region of the first Group III-nitride layer so as to bridge between two laterally grown regions of the first Group III-nitride layer.  
   
   
       69 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and wherein a portion of the source contact is disposed on a second laterally grown region adjacent the first laterally grown region.  
   
   
       70 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and wherein the source contact extends to but not beyond a second laterally grown region adjacent the first laterally grown region.  
   
   
       71 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and wherein the source contact does not extend to a second laterally grown region adjacent the first laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       72 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and wherein a portion of the source contact is disposed on the second laterally grown region.  
   
   
       73 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and wherein the source contact extends to but not beyond the second laterally grown region.  
   
   
       74 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and wherein the source contact does not extend to the second laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       75 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact and wherein a portion of the source contact is disposed on the first laterally grown region.  
   
   
       76 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact and wherein the source contact extends to but not beyond the first laterally grown region.  
   
   
       77 . The method of  claim 54 , wherein the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact and wherein the source contact does not extend to the first laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer.  
   
   
       78 . The method of  claim 54 , wherein the first Group III-nitride layer is semi-insulating or insulating.  
   
   
       79 . The method of  claim 78 , wherein forming a first Group III-nitride layer comprises forming a GaN based layer incorporated deep level dopants.  
   
   
       80 . The method of  claim 79 , wherein the deep level dopants comprise Fe.  
   
   
       81 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is provided extends from beneath the source contact to beneath the drain contact.  
   
   
       82 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is provided extends from beneath the gate contact to beneath the drain contact.  
   
   
       83 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is provided extends from beneath the gate contact toward but not to beneath the drain contact.  
   
   
       84 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is provided extends from beneath the source contact toward but not to beneath the drain contact.  
   
   
       85 . The method of  claim 54 , wherein the laterally grown region on which the gate contact is provided extends a majority of the distance from source contact to the drain contact.  
   
   
       86 . The method of  claim 54 , wherein the first Group III-nitride layer is provided on a substrate, the method further comprising forming a trench in the substrate and wherein the laterally grown regions extend over the trench.  
   
   
       87 . The method of  claim 86 , wherein the substrate comprises a silicon carbide substrate and wherein forming a trench comprises forming a trench that extends perpendicular or parallel to a crystal plane of the silicon carbide substrate.  
   
   
       88 . The method of  claim 87 , wherein the crystal plane of the silicon carbide substrate is a plane in the {11{overscore (2)}0} family of planes or the {10{overscore (1)}0} family of planes.  
   
   
       89 . The method of  claim 86 , further comprising forming a mask layer in the trench.  
   
   
       90 . The method of  claim 87 , wherein the laterally grown regions have substantially vertical growth sidewalls.  
   
   
       91 . The method of  claim 87 , wherein the laterally grown regions have trapezoidal growth sidewalls.  
   
   
       92 . The method of  claim 54 , wherein the first Group III-nitride layer is provided on a substrate, the method further comprising forming a mask pattern on the substrate and wherein forming a first Group III-nitride layer comprises forming a first Group III-nitride layer on the substrate and the mask pattern such that the laterally grown regions extend over the mask pattern.  
   
   
       93 . The method of  claim 54 , wherein the source contact, the gate contact and the drain contact each comprise a plurality of contact fingers and wherein the laterally grown regions comprise a plurality of laterally grown regions separated by vertically grown regions, where each gate contact finger is provided on a corresponding one of the plurality of laterally grown regions.  
   
   
       94 . The method of  claim 86 , wherein the trench comprises a plurality of trenches, the source contact, the gate contact and the drain contact each comprise a plurality of contact fingers and where each gate contact finger is disposed above a corresponding one of the plurality of trenches.  
   
   
       95 . A method of fabricating a semiconductor device, comprising: 
 forming a Group III-nitride layer on a silicon carbide die, the Group III-nitride layer having at least one vertically grown region and at least one laterally grown region;    forming at least one Group III-nitride transistor on the silicon carbide die; and    wherein the at least one laterally grown region does not extend substantially beyond a region of the silicon carbide die corresponding to the at least one Group III-nitride transistor.    
   
   
       96 . The method of  claim 95 , wherein the at least one Group III-nitride transistor comprises a plurality of gate fingers and wherein the at least one laterally grown region comprises a plurality of laterally grown regions disposed beneath respective ones of the gate fingers of the at least on Group III-nitride transistor.  
   
   
       97 . The method of  claim 95 , wherein the at least one Group III-nitride transistor comprises a plurality Group-Ill nitride transistors and wherein the at least one laterally grown region comprises a plurality of laterally grown regions corresponding to respective ones of the plurality of Group III-nitride transistors.  
   
   
       98 . The method of  claim 95 , wherein the silicon carbide die comprises a portion of a silicon carbide wafer.  
   
   
       99 . The method of  claim 98 , wherein the silicon carbide wafer includes a major flat and wherein the at least one laterally grown region has a boundary with a vertically grown region that is perpendicular or parallel to the major flat.  
   
   
       100 . The method of  claim 95 , wherein the at least one Group III-nitride transistor comprises a gallium nitride-based high electron mobility transistor (HEMT).  
   
   
       101 . The method of  claim 95 , further comprising forming at least one Group III-nitride transistor on the silicon carbide die in a region of the die other than the region of the die with the at least one laterally grown region.  
   
   
       102 . The method of  claim 95 , further forming comprising at least one capacitor, resistor and/or inductor on the silicon carbide die in a region of the die other than the region of the die with the at least one laterally grown region.  
   
   
       103 . The method of  claim 95 , wherein the at least one laterally grown region has a boundary with a vertically grown region that is aligned perpendicular or parallel to a crystal plane of the silicon carbide substrate.  
   
   
       104 . The method of  claim 102 , wherein the crystal plane of the silicon carbide substrate is a plane in the {11{overscore (2)}0} family of planes or the {10{overscore (1)}0} family of planes.