Raised-lines overlay semiconductor targets and method of making the same

Abstract

The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.

1 . An overlay target on a wafer comprising: 
 a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the plurality of raised lines of the overlay target.    
   
   
       2 . The overlay target of  claim 1 , further comprising: 
 at least one trench comprising a continuous trench defining a geometric shape.    
   
   
       3 . The overlay target of  claim 1 , further comprising: 
 at least one trench comprising a plurality of trenches defining said overlay target, each of said plurality of trenches includes a series of raised lines.    
   
   
       4 . The overlay target of  claim 3 , wherein said plurality of trenches includes at least one continuous trench defining a geometric shape.  
   
   
       5 . The overlay target of  claim 1 , wherein said plurality of raised lines comprises raised lines etched into said wafer.  
   
   
       6 . The overlay target of  claim 5 , wherein said plurality of raised lines comprise raised lines etched into a material layer overlying said wafer.  
   
   
       7 . The overlay target of  claim 5 , wherein said plurality of raised lines comprise raised lines disposed in at least one trench.  
   
   
       8 . The overlay target  claim 5 , wherein a plurality of trenches and a corresponding plurality of series of raised lines define said overlay target, each of said plurality of trenches including at lest one of said plurality of series of raised lines.  
   
   
       9 . The overlay target of  claim 5 , wherein said plurality of raised lines comprises raised lines disposed in at least one pad area.  
   
   
       10 . The overlay target of  claim 9 , wherein a plurality of pad areas and a corresponding plurality of series of raised lines define said overlay target, each of said plurality of pad areas including at least one of said plurality of series of raised lines.  
   
   
       11 . The overlay target of  claim 5 , wherein said plurality of raised lines comprises a first series of raised lines disposed in a pad area and a second series of raised lines disposed in a trench.  
   
   
       12 . An overlay target on a wafer for use in a semiconductor manufacturing process comprising: 
 a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the plurality of raised lines of the overlay target.    
   
   
       13 . The overlay target of  claim 12 , further comprising: 
 at least one trench comprising a continuous trench defining a geometric shape.    
   
   
       14 . The overlay target of  claim 12 , further comprising: 
 at least one trench comprising a plurality of trenches defining said overlay target, each of said plurality of trenches includes a series of raised lines.    
   
   
       15 . The overlay target of  claim 14 , wherein said plurality of trenches includes at least one continuous trench defining a geometric shape.  
   
   
       16 . An overlay target formed on a wafer in a manufacturing process comprising: 
 a plurality of raised lines in the wafer covered by a layer of material forming a target for allowing registration of the wafer using the plurality of raised lines of the overlay target.    
   
   
       17 . The overlay target of  claim 16 , further comprising: 
 at least one trench comprising a continuous trench defining a geometric shape.    
   
   
       18 . The overlay target of  claim 16 , further comprising: 
 at least one trench comprising a plurality of trenches defining said overlay target, each of said plurality of trenches includes a series of raised lines.    
   
   
       19 . The overlay target of  claim 18 , wherein said plurality of trenches includes at least one continuous trench defining a geometric shape.