Substrates including alignment fences

Abstract

A substrate includes a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, therewith. The fence may include a plurality of adjacent, mutually adhered regions, which may comprise layers. One or more laterally recessed regions may be located at one or more corners of a receptacle formed by the fence to facilitate rough alignment of a semiconductor device with the substrate. The receptacle of the fence may include edges that are configured to progressively align a semiconductor device with the substrate.

1 . A substrate configured to have a semiconductor device at least temporarily electrically connected thereto, comprising: 
 a substantially planar member;    a first array of contacts exposed at a surface of the substantially planar member; and    a fence positioned on the surface, at least partially around the first array of contacts, the fence including a plurality of adjacent, mutually adhered regions forming a receptacle for receiving the semiconductor device.    
   
   
       2 . The substrate of  claim 1 , wherein the plurality of adjacent, mutually adhered regions comprises a plurality of at least partially superimposed, contiguous, mutually adhered layers.  
   
   
       3 . The substrate of  claim 1 , wherein each of the plurality of adjacent, mutually adhered regions comprises dielectric material.  
   
   
       4 . The substrate of  claim 3 , wherein the dielectric material comprises a polymer.  
   
   
       5 . The substrate of  claim 4 , wherein the polymer comprises a photopolymer.  
   
   
       6 . The substrate of  claim 1 , wherein the fence comprises at least one protective layer extending over at least a portion of at least one of the surface and another, opposite surface of the substantially planar member.  
   
   
       7 . The substrate of  claim 1 , wherein the contacts of the first array comprise conductive structures that protrude above the surface.  
   
   
       8 . The substrate of  claim 1 , wherein the receptacle comprises tapered walls configured to progressively guide bond pads or conductive structures of a semiconductor device introduced into the receptacle into alignment with corresponding contacts of the first array.  
   
   
       9 . The substrate of  claim 1 , wherein selected contacts of the first array are recessed below the surface.  
   
   
       10 . The substrate of  claim 9 , further comprising: 
 at least one knife-edged spine protruding into a recess above each of the selected contacts, the at least one knife-edged spine being configured to pierce a conductive structure of the semiconductor device upon assembly with the substrate.    
   
   
       11 . The substrate of  claim 10 , wherein the at least one knife-edged spine comprises metal or a metallized surface.  
   
   
       12 . The substrate of  claim 11 , wherein metal of the at least one knife-edged spine communicates with a corresponding one of the selected contacts.  
   
   
       13 . The substrate of  claim 1 , wherein the fence extends onto at least a portion of at least one peripheral edge of the substantially planar member.  
   
   
       14 . A substrate configured to have a semiconductor device at least temporarily electrically connected thereto, comprising: 
 a substantially planar member;    a first array of contacts exposed at a surface of the substantially planar member; and    a fence including a receptacle for receiving the semiconductor device, the receptacle including at least one laterally recessed area in a corner thereof for receiving a corner of a semiconductor device.    
   
   
       15 . The substrate of  claim 14 , wherein the at least one laterally recessed area is configured to facilitate rough alignment of the semiconductor device with the substrate.  
   
   
       16 . The substrate of  claim 14 , wherein the fence includes at least two laterally recessed areas at corners of the receptacle.  
   
   
       17 . The substrate of  claim 16 , wherein the at least two laterally recessed areas are located at opposite corners of the receptacle.  
   
   
       18 . The substrate of  claim 14 , wherein the fence comprises at least one protective layer extending over at least a portion of at least one of the surface and another, opposite surface of the substantially planar member.  
   
   
       19 . The substrate of  claim 14 , wherein the contacts of the first array comprise conductive structures that protrude above the surface.  
   
   
       20 . The substrate of  claim 14 , wherein the receptacle comprises tapered walls configured to progressively guide bond pads or conductive structures of a semiconductor device introduced into the receptacle into alignment with corresponding contacts of the first array.  
   
   
       21 . The substrate of  claim 14 , wherein selected contacts of the first array are recessed below the surface.  
   
   
       22 . The substrate of  claim 21 , further comprising: 
 at least one knife-edged spine protruding into a recess above each of the selected contacts, the at least one knife-edged spine being configured to pierce a conductive structure of the semiconductor device upon assembly with the substrate.    
   
   
       23 . The substrate of  claim 22 , wherein the at least one knife-edged spine comprises metal or a metallized surface.  
   
   
       24 . The substrate of  claim 23 , wherein metal of the at least one knife-edged spine communicates with a corresponding one of the selected contacts.  
   
   
       25 . The substrate of  claim 14 , wherein the fence extends onto at least a portion of at least one peripheral edge of the substantially planar member.