Chip-scale packages

Abstract

Improved chip-scale packages wherein semiconductor die side surfaces are free of the material defects associated with prior art chip-scale package formation. In one embodiment, chip-scale package includes a semiconductor die includes an active surface, an opposing passive surface, and a plurality of etched side surfaces extending from the active surface to the passive surface. A first protective coating may extend over the active surface of the semiconductor die and a second protective coating may extend over the passive surface of the semiconductor die wherein one of the first protective coating and the second protective coating extends over the plurality of etched side surfaces of the semiconductor die.

1 . A chip-scale package, comprising: 
 a semiconductor die having an active surface, an opposing passive surface, and a plurality of etched side surfaces extending from the active surface to the passive surface;    a first protective coating extending over the active surface of the semiconductor die; and    a second protective coating extending over the passive surface of the semiconductor die wherein one of the first protective coating and the second protective coating extends over the plurality of etched side surfaces of the semiconductor die.    
   
   
       2 . The chip-scale package of  claim 1 , wherein the first protective coating extends over the plurality of etched side surfaces of the semiconductor die.  
   
   
       3 . The chip-scale package of  claim 2 , wherein a portion of the first protective coating protrudes beyond the passive surface of the semiconductor die and a portion of the second protective coating is adhered to a side of the portion of the first protective coating protruding beyond the passive surface of the semiconductor die.  
   
   
       4 . The chip-scale package of  claim 1 , wherein the second protective coating extends over the plurality of etched side surfaces of the semiconductor die.  
   
   
       5 . The chip-scale package of  claim 1 , wherein at least one of the first protective coating and the second protective coating comprises a polymer sealant material.  
   
   
       6 . The chip-scale package of  claim 5 , wherein the polymer sealant material comprises a photocurable polymer sealant material.