Method of manufacturing semiconductor mos transistor device

Abstract

A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

1 . A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device, comprising: 
 providing a semiconductor substrate having a main surface;    forming a gate dielectric layer on the main surface;    forming a gate electrode on the gate dielectric layer, wherein the gate electrode has vertical sidewalls and a top surface;    forming a liner on the vertical sidewalls of the gate electrode;    forming a silicon nitride spacer on the liner;    ion implanting the main surface using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface;    removing the silicon nitride spacer; and    forming a cap layer that borders the liner, wherein the cap layer has a specific stress status.    
   
   
       2 . The method of manufacturing a MOS transistor device according to  claim 1  wherein the liner is made of silicon oxide.  
   
   
       3 . The method of manufacturing a MOS transistor device according to  claim 1  wherein the cap layer is made of silicon nitride.  
   
   
       4 . The method of manufacturing a MOS transistor device according to  claim 1  further comprising the step of forming a source/drain extension under the liner.  
   
   
       5 . The method of manufacturing a MOS transistor device according to  claim 1  further comprising the step of forming a salicide layer on the source/drain region.  
   
   
       6 . The method of manufacturing a MOS transistor device according to  claim 1  further comprising the step of annealing the source/drain region.  
   
   
       7 . The method of manufacturing a MOS transistor device according to  claim 1  wherein the cap layer has a thickness of about 30˜2000 angstroms.  
   
   
       8 . The method of manufacturing a MOS transistor device according to  claim 1  wherein the cap layer acts as an etching stop layer during etching of a contact hole.  
   
   
       9 . The method of manufacturing a MOS transistor device according to  claim 1  wherein the MOS transistor device is an NMOS transistor device and wherein the cap layer is tensile-stressed.  
   
   
       10 . The method of manufacturing a MOS transistor device according to  claim 1  wherein the MOS transistor device is a PMOS transistor device and wherein the cap layer is compressive-stressed.  
   
   
       11 . A metal-oxide-semiconductor (MOS) transistor device, comprising: 
 a semiconductor substrate having a main surface;    a gate dielectric layer on the main surface;    a gate electrode on the gate dielectric layer, wherein the gate electrode has vertical sidewalls and a top surface;    an L-shaped liner on the vertical sidewalls of the gate electrode;    a source region in the main surface; and    a drain region separated from the source region by a channel region under the gate electrode, wherein the source region and the drain region define a channel direction, and wherein the channel region is strained in the channel direction by a stressed cap layer, which borders the L-shaped liner.    
   
   
       12 . The MOS transistor device according to  claim 11  wherein the MOS transistor device is an NMOS transistor device and wherein the stressed cap layer is tensile-stressed.  
   
   
       13 . The MOS transistor device according to  claim 11  wherein the MOS transistor device is a PMOS transistor device and wherein the stressed cap layer is compressive-stressed.  
   
   
       14 . The MOS transistor device according to  claim 11  wherein the semiconductor substrate is silicon substrate.  
   
   
       15 . The MOS transistor device according to  claim 11  wherein the liner comprises silicon oxide.  
   
   
       16 . The MOS transistor device according to  claim 11  further comprising a salicide layer on the source region and the drain region.  
   
   
       17 . The MOS transistor device according to  claim 11  wherein the stressed cap layer has a thickness of about 30˜2000 angstroms.  
   
   
       18 . The MOS transistor device according to  claim 11  wherein the cap layer covers the source region, the drain region, the liner, and the top surface of the gate electrode.  
   
   
       19 . The MOS transistor device according to  claim 11  wherein the cap layer is made of silicon nitride.  
   
   
       20 . The MOS transistor device according to  claim 11  wherein the cap layer is made of silicon oxide.  
   
   
       21 . The MOS transistor device according to  claim 11  wherein the cap layer is further laminated by at least one dielectric layer.  
   
   
       22 . The MOS transistor device according to  claim 21  wherein the dielectric layer is stressed.  
   
   
       23 . The MOS transistor device according to  claim 21  wherein the MOS transistor device is NMOS transistor device and the dielectric layer is tensile-stressed.  
   
   
       24 . The MOS transistor device according to  claim 21  wherein the MOS transistor device is PMOS transistor device and the dielectric layer is compressive-stressed.  
   
   
       25 . The MOS transistor device according to  claim 11  wherein the liner has a thickness of about 0 to 500 angstroms.