US2006113675A1PendingUtilityA1

Barrier material and process for Cu interconnect

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Assignee: CHANG CHUNG-LIANGPriority: Dec 1, 2004Filed: Dec 1, 2004Published: Jun 1, 2006
Est. expiryDec 1, 2024(expired)· nominal 20-yr term from priority
Inventors:Chung-Liang ChangChing-Hua HsiehShau-Lin Shue
H10W 20/0425H10W 20/47H10W 20/0526H10W 20/425H10W 20/096H10W 20/095H10W 20/081H10W 20/077H10W 20/056H10W 20/48H10W 20/043H10W 20/037H10W 20/035
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Claims

Abstract

A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device having enhanced electromigration performance, the device comprising: 
 a low-k dielectric layer, the low-k dielectric layer having a surface with a recessed feature;    a diffusion barrier layer on the surface of the low-k dielectric layer;    a glue layer on the diffusion barrier layer; and    a conductor on the glue layer, the conductor filling the recessed feature.    
   
   
       2 . The semiconductor device of  claim 1 , further including a cap layer on the conductor, wherein the cap layer is selected from the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the diffusion barrier layer includes a first barrier layer on the surface of the low-k dielectric layer and a second barrier layer on the first barrier layer.  
   
   
       4 . The semiconductor device of  claim 3 , wherein the first barrier layer is selected from the group consisting essentially of Ta, W, and combinations thereof.  
   
   
       5 . The semiconductor device of  claim 3 , wherein the second barrier layer is selected from the group consisting essentially of Ni, Co, Al, AlCu alloy, W, Ti, Ta, Ra, Ru, and combinations thereof.  
   
   
       6 . The semiconductor device of  claim 3 , wherein the second barrier layer is selected from the group consisting essentially of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.  
   
   
       7 . The semiconductor device of  claim 1 , wherein the diffusion barrier layer is selected from the group consisting essentially of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.  
   
   
       8 . The semiconductor device of  claim 7 , wherein the diffusion barrier layer is metal rich.  
   
   
       9 . The semiconductor device of  claim 7 , wherein the diffusion barrier layer further includes a metal rich surface.  
   
   
       10 . The semiconductor device of  claim 7 , wherein the diffusion barrier layer further includes a thermal treatment to enhance adhesion.  
   
   
       11 . The semiconductor device of  claim 1 , wherein the diffusion barrier layer is about 10 to 30 Angstroms.  
   
   
       12 . The semiconductor device of  claim 1 , wherein the low-k dielectric layer comprises C, O, Si, and F.  
   
   
       13 . The semiconductor device of  claim 2 , wherein the cap layer is selected from the group consisting essentially of a carbon-containing dielectric, a nitrogen-containing dielectric, a nitrogen-containing conductor, a silicon-containing conductive layer, and silicon, and combinations thereof.  
   
   
       14 . The semiconductor device of  claim 1 , wherein the glue layer is selected from the group consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.  
   
   
       15 . The semiconductor device of  claim 14 , wherein a thickness ratio of the glue layer to the diffusion barrier layer is about 1 to 50.  
   
   
       16 . The semiconductor device of  claim 14 , wherein a thickness of the glue layer is about 10 to 500 Angstroms.  
   
   
       17 . The semiconductor device of  claim 14 , wherein the metal-rich nitride comprises TaN and wherein an atomic ratio of nitrogen to tantalum is less than about 1.  
   
   
       18 . The semiconductor device of  claim 1 , wherein the conductor is selected from the group consisting essentially of Cu, Al, Au, and Ag, and combinations thereof.  
   
   
       19 . A method of reducing electromigration effects in a copper damascene device, the method comprising: 
 forming a low-k dielectric layer, the low-k dielectric layer having a surface with a recessed feature;    forming a diffusion barrier layer over the surface of the low-k dielectric layer;    forming a glue layer upon the diffusion barrier layer;    filing the recessed feature with a conductor;    annealing the conductor; and    forming a cap layer upon the conductor.    
   
   
       20 . The method of  claim 19 , wherein the cap layer is selected from the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof.  
   
   
       21 . The method of  claim 19 , wherein the diffusion barrier layer is selected from the group consisting essentially of TaN, TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.  
   
   
       22 . The method of  claim 19 , wherein the diffusion barrier layer is about 10 to 30 Angstroms.  
   
   
       23 . The method of  claim 19 , wherein the cap layer is selected from the group consisting essentially of a carbon-containing dielectric, a nitrogen-containing dielectric, a nitrogen-containing conductor, a silicon-containing conductive layer, and silicon, and combinations thereof.  
   
   
       24 . The method of  claim 19 , further including thermally treating the diffusion barrier layer.  
   
   
       25 . The method of  claim 19 , wherein the glue layer is selected from the group consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.  
   
   
       26 . The method of  claim 25 , wherein the glue layer is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).  
   
   
       27 . The method of  claim 25 , wherein a thickness ratio of the glue layer to the diffusion barrier layer is about 1 to 50.  
   
   
       28 . The method of  claim 25 , wherein a thickness of the glue layer is about 10 to 500 Angstroms.  
   
   
       29 . The method  claim 25 , wherein the metal-rich nitride comprises TaN and wherein an atomic ratio of nitrogen to tantalum is less than about 1.  
   
   
       30 . The method of  claim 19 , wherein the conductor annealing step comprises annealing at about 150 to 450° C. for about 0.5 to 5 minutes in forming gas.  
   
   
       31 . The method of  claim 19 , wherein the diffusion barrier layer is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).  
   
   
       32 . The method of  claim 19 , wherein the cap layer is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or plasma enhanced atomic layer deposition (PEALD).  
   
   
       33 . A method for forming a semiconductor device, comprising: 
 providing a substrate, the substrate including a low-k dielectric layer with an opening;    performing a pore sealing process;    forming a barrier layer within the opening;    forming a glue layer on the barrier layer;    forming a seed layer on the glue layer;    forming a conductor on the seed layer;    and forming a cap layer on the conductor.    
   
   
       34 . The method of  claim 33 , wherein the cap layer is selected from the group consisting essentially of Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof.  
   
   
       35 . The method of  claim 33 , wherein the barrier layer is selected from the group consisting essentially of TaN, TiN, WN, ThN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof.  
   
   
       36 . The method of  claim 33 , wherein the barrier layer is about 10 to 30 Angstroms.  
   
   
       37 . The method of  claim 33 , wherein the cap layer is selected from the group consisting essentially of a carbon-containing dielectric, a nitrogen-containing dielectric, a nitrogen-containing conductor, a silicon-containing conductive layer, and silicon, and combinations thereof.  
   
   
       38 . The method of  claim 33 , wherein the glue layer is selected from the group consisting essentially of a metal-rich nitride, Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and combinations thereof.  
   
   
       39 . The method of  claim 33 , wherein a thickness ratio of the glue layer to the barrier layer is about 1 to 50.  
   
   
       40 . The method of  claim 33 , wherein a thickness of the glue layer is about 10 to 500 Angstroms.  
   
   
       41 . The method  claim 38 , wherein the metal-rich nitride comprises TaN and wherein an atomic ratio of nitrogen to tantalum is less than about 1.  
   
   
       42 . The method of  claim 33 , further comprising annealing the conductor at about 150 to 450° C. for about 0.5 to 5 minutes in forming gas.  
   
   
       43 . The method of  claim 33 , wherein the pore sealing process comprises vapor pore sealing.

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