US2006115932A1PendingUtilityA1

Method for fabricating semiconductor components with conductive vias

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Assignee: FARNWORTH WARREN MPriority: Dec 18, 1997Filed: Jan 17, 2006Published: Jun 1, 2006
Est. expiryDec 18, 2017(expired)· nominal 20-yr term from priority
Inventors:Warren M. FarnworthAlan G. WoodDavid R. Hembree
H05K 3/0029H05K 1/112H05K 2201/09827H05K 2201/09472H05K 2201/10734H05K 2201/09845H05K 1/0306H05K 3/0032H05K 2201/0959H05K 2201/10674H10W 20/0245H10W 20/0238H10W 90/297H10W 90/20H10W 90/722H10W 74/15H10W 72/0711H10W 72/9445H10W 72/90H10W 72/9415H10W 72/942H10W 72/9226H10W 72/923H10W 90/00H10W 72/07236H10W 70/093H10W 90/724H10W 72/252H10W 72/251H10P 72/74H10W 70/635H10W 70/614H10W 70/68H10W 20/023H10W 20/20H10W 70/095
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Claims

Abstract

A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

Claims

exact text as granted — not AI-modified
1 . A method for fabricating a semiconductor component comprising: 
 providing a substrate comprising a first side, a substrate contact on the first side, and an opposing second side;    forming an opening through the substrate contact;    forming a via at least partially aligned with the opening through the substrate to the second side; and    forming a conductive member in the opening and the via in electrical contact with the substrate contact.    
     
     
         2 . The method of  claim 1  wherein the forming the conductive member step comprises electroless deposition or electrolytic deposition of a metal into the opening and the via.  
     
     
         3 . The method of  claim 1  wherein the forming the conductive member step comprises depositing a conductive polymer into the opening and the via.  
     
     
         4 . The method of  claim 1  wherein the forming the opening step comprises etching the substrate contact.  
     
     
         5 . The method of  claim 1  wherein the forming the via step comprises laser machining the substrate.  
     
     
         6 . The method of  claim 1  wherein the forming the via step comprises etching.  
     
     
         7 . The method of  claim 1  further comprising forming an insulating layer on a surface of the via prior to the forming the conductive member step.  
     
     
         8 . The method of  claim 1  wherein the conductive member fills the via.  
     
     
         9 . The method of  claim 1  wherein the conductive member comprises a layer on a sidewall of the via.  
     
     
         10 . The method of  claim 1  wherein the substrate comprises a semiconductor die and the substrate contact comprises a pad in electrical communication with at least one integrated circuit on the substrate.  
     
     
         11 . The method of  claim 1  wherein the substrate comprises a semiconductor die and the substrate contact comprises a bond pad or a redistribution pad in electrical communication with at least one integrated circuit on the die.  
     
     
         12 . The method of  claim 1  wherein the conductive member comprises a metal, a solder or a conductive polymer.  
     
     
         13 . The method of  claim 1  further comprising forming a non oxidizing metal layer on a terminal portion of the conductive member.  
     
     
         14 . The method of  claim 1  further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.  
     
     
         15 . The method of  claim 1  wherein the forming the conductive member step forms generally concave terminal portions on the conductive member.  
     
     
         16 . A method for fabricating a semiconductor component comprising: 
 providing a semiconductor substrate comprising a first side, a substrate contact on the first side in electrical communication with an integrated circuit on the substrate, and an opposing second side;    forming an opening through the substrate contact;    forming a via at least partially aligned with the opening through the substrate to the second side;    forming an insulating layer on a surface of the via; and    forming a conductive material in the opening and the via in electrical contact with the substrate contact.    
     
     
         17 . The method of  claim 16  wherein the forming the conductive material step comprises electroless deposition, CVD or electrolytic deposition.  
     
     
         18 . The method of  claim 16  wherein the forming the insulating layer step comprises depositing an oxide, a nitride or a polymer material on the surface.  
     
     
         19 . The method of  claim 16  further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.  
     
     
         20 . The method of  claim 16  wherein the substrate contact comprises a bond pad or a redistribution pad.  
     
     
         21 . The method of  claim 16  wherein the substrate comprises a plurality of substrate contacts and the forming the opening step forms a plurality of openings, the forming the vias step forms a plurality of vias, the forming the insulating layer step forms a plurality of insulating layers, and the forming the conductive member step forms a plurality of conductive members.  
     
     
         22 . The method of  claim 16  wherein the conductive member fills the via.  
     
     
         23 . The method of  claim 16  wherein the conductive member comprises a layer on a sidewall of the via.  
     
     
         24 . The method of  claim 16  wherein the conductive member comprises a metal, a solder or a conductive polymer.  
     
     
         25 . The method of  claim 16  further comprising forming a non oxidizing metal layer on a terminal portion of the conductive member.  
     
     
         26 . The method of  claim 16  further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.  
     
     
         27 . The method of  claim 16  wherein the forming the opening step comprises etching the substrate contact.  
     
     
         28 . The method of  claim 16  wherein the forming the via step comprises laser machining the substrate.  
     
     
         29 . The method of  claim 16  wherein the forming the via step comprises etching.  
     
     
         30 . A method for fabricating a semiconductor component comprising: 
 providing a substrate comprising a first side, a substrate contact on the first side, and an opposing second side;    forming an opening through the substrate contact;    forming a via part way through the substrate at least partially aligned with the opening;    forming a conductive member in the opening and the via in electrical contact with the substrate contact; and    thinning the substrate from the second side to expose the conductive member.    
     
     
         31 . The method of  claim 30  wherein the forming the conductive member step comprises a method selected from the group consisting of electroless deposition, CVD, electrolytic deposition, screen printing, and stenciling.  
     
     
         32 . The method of  claim 30  wherein the thinning the substrate step comprises a method selected from the group consisting of planarization, chemical mechanical planarization and etching.  
     
     
         33 . The method of  claim 30  wherein the substrate comprises a semiconductor die and the substrate contact comprises a pad in electrical communication with at least one integrated circuit on the substrate.  
     
     
         34 . The method of  claim 30  wherein the forming the opening step comprises etching.  
     
     
         35 . The method of  claim 30  wherein the forming the via step comprises laser machining and etching.  
     
     
         36 . The method of  claim 30  wherein the substrate comprises a semiconductor die and the substrate contact comprises a bond pad or a redistribution pad.  
     
     
         37 . The method of  claim 30  further comprising forming a first external contact on the first side in electrical communication with the conductive member.  
     
     
         38 . The method of  claim 37  further comprising forming a first non oxidizing layer on the first external contact.  
     
     
         39 . The method of  claim 30  further comprising forming a second external contact on the second side in electrical communication with the conductive member.  
     
     
         40 . The method of  claim 39  further comprising forming a second non oxidizing layer on the second external contact.

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