Byte-operational nonvolatile semiconductor memory device

Abstract

Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

1 . An apparatus comprising a memory cell, wherein the memory cell comprises: 
 a plurality of first transistors configured to store data; and    a second transistor configured to activate the plurality of first transistors at the same time, wherein: 
 a source or a drain of each of the plurality of first transistors is connected to a source or a drain of the second transistor;  
 the resistance of each connection between each of the plurality of first transistors and the second transistor is substantially the same.  
   
   
   
       2 . The apparatus of  claim 1 , wherein the length of each connection between each of the plurality of first transistors and the second transistor is substantially the same.  
   
   
       3 . The apparatus of  claim 2 , wherein the length of each connection between each of the plurality of first transistors and the second transistor is minimized.  
   
   
       4 . The apparatus of  claim 1 , wherein: 
 the plurality of first transistors are arranged parallel to each other in a row;    a channel of the second transistor is substantially parallel to each channel of each of the plurality of first transistors.    
   
   
       5 . The apparatus of  claim 4 , wherein the channel width of the second transistor extends approximately the length of the row of the plurality of first transistors.  
   
   
       6 . The apparatus of  claim 5 , wherein each connection between each of the plurality of first transistors and the second transistor is at a different point along the source or the drain of the second transistor.  
   
   
       7 . The apparatus of  claim 1 , wherein the apparatus is comprised in a NOR-type flash memory device utilizing source side injection during operation.  
   
   
       8 . The apparatus of  claim 1 , wherein the plurality of first transistors comprise at least three transistors.  
   
   
       9 . The apparatus of  claim 8 , wherein the plurality of first transistors comprise eight transistors.