Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same

Abstract

A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer. A metal barrier layer is formed on the resist layer and in the holes. A patterned circuit layer is electroplated in the holes of the resist layer after removing the metal barrier layer on the resist layer. The resist layer and the metal conductive layer underneath the resist layer are removed. Another metal barrier layer can be formed on the circuit layer. The patterned circuit layer is covered by the metal barrier layers to prevent damage from etching to the circuit layer and inhibit migration of metal particles in the circuit layer.

1 - 9 . (canceled)  
   
   
       10 . A circuit barrier structure of a semiconductor packaging substrate, comprising: 
 a metal conductive layer formed on a surface of the substrate having inner circuits and an insulating layer;    a patterned circuit layer electroplated on the metal conductive layer; and    a metal barrier layer formed on sides and the bottom of the patterned circuit layer.    
   
   
       11 . The circuit barrier structure of  claim 10 , further comprising another metal barrier layer formed on the top of the patterned circuit layer.  
   
   
       12 . The circuit barrier structure of  claim 10 , further comprising: 
 a solder mask layer formed on the surface of the substrate, the solder mask layer being patterned to have a plurality of openings to expose electrical connection pads of the circuit layer; and    a metal protection layer formed in the openings of the solder mask layer and on the exposed electrical connection pads respectively.    
   
   
       13 . The circuit barrier structure of  claim 12 , wherein the metal protection layer is made of a material selected from the group consisting of Au, Ni, Pd, Ag, Sn, Ni/Pd, Cr/Ti, Ni/Au, Pd/Au, and Ni/Pd/Au.  
   
   
       14 . The circuit barrier structure of  claim 10 , further comprising: 
 a metal protection layer formed on the circuit layer to cover electrical connection pads of the circuit layer; and    a solder mask layer formed on the surface of the substrate, the solder mask layer being patterned to have a plurality of openings to expose the electrical connection pads.    
   
   
       15 . The circuit barrier structure of  claim 14 , wherein the metal protection layer is made of a material selected from the group consisting of Au, Ni, Pd, Ag, Sn, Ni/Pd, Cr/Ti, Ni/Au, Pd/Au, and Ni/Pd/Au.  
   
   
       16 . The circuit barrier structure of  claim 10 , wherein the metal barrier layer is made of a material selected from the group consisting of Cr, Ni, Co, Pd, Ta, and Ti.