Chip scale package and method for manufacturing the same

Abstract

A chip scale package includes a patterned circuit layer attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive layer such that contact pads on a lower surface of the patterned circuit layer are electrically coupled to corresponding bonding pads on the semiconductor chip. The patterned circuit layer has a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening. A plurality of metal bumps are respectively disposed in the openings and mounted to the exposed portions of the contact pads for making external electrical connection. The present invention further provides a method for manufacturing the chip scale package at the wafer-level.

1 . A chip scale package comprising: 
 a semiconductor chip having a plurality of bonding pads formed on an active surface thereof;    a patterned circuit layer having a plurality of contact pads on a lower surface thereof and a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening;    the lower surface of patterned circuit layer attached to the active surface of the semiconductor chip through an anisotropic conductive adhesive layer such that the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip; and    a plurality of metal bumps respectively disposed in the openings of the patterned circuit layer and mounted to the exposed portions of the contact pads of the patterned circuit layer for making external electrical connection.    
   
   
       2 . The chip scale package as claimed in  claim 1 , wherein the contact pads are formed at locations corresponding to the bonding pads on the semiconductor chip.  
   
   
       3 . The chip scale package as claimed in  claim 2 , wherein the anisotropic conductive adhesive layer is formed from an adhesive filled with a plurality of conductive particles, and the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles.  
   
   
       4 . The chip scale package as claimed in  claim 1 , wherein the patterned circuit layer includes a plurality of conductive traces each having a first end portion formed at a location corresponding to one of the bonding pads on the semiconductor chip and a second end portion serving as the contact pad.  
   
   
       5 . The chip scale package as claimed in  claim 4 , wherein the anisotropic conductive adhesive layer is formed from an adhesive filled with a plurality of conductive particles, and the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles and the conductive traces.  
   
   
       6 . A chip scale package comprising: 
 a semiconductor chip having a plurality of bonding pads formed on an active surface thereof;    a patterned circuit layer having opposing upper and upper surfaces, the patterned circuit layer having a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to the corresponding solder pads;    the lower surface of patterned circuit layer attached to the active surface of the semiconductor chip through an anisotropic conductive adhesive layer having a plurality of conductive particles such that the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles; and    a plurality of metal bumps respectively mounted to the solder pads of the patterned circuit layer for making external electrical connection.    
   
   
       7 . A method for manufacturing chip scale packages at the wafer-level, the method comprising steps of: 
 providing a tape circuit including a plurality of contact pads on a lower surface of a tape;    providing a wafer including a plurality of semiconductor chips wherein each semiconductor chip has a plurality of bonding pads on an active surface thereof;    forming an anisotropic conductive adhesive layer onto the active surface of the wafer;    attaching the tape circuit onto the wafer through the anisotropic conductive adhesive layer to form a tape-circuit/wafer assembly such that the contact pads are electrically coupled to the corresponding bonding pads on the semiconductor chip;    removing the tape from the tape-circuit/wafer assembly and exposing the contact pads;    forming an insulating layer over the tape-circuit/wafer assembly and patterning the insulating layer to form a plurality of openings at locations corresponding to the contact pads after the tape being removed;    forming a plurality of metal bumps in the openings of the insulating layer and mounted to the contact pads; and    conducting a cutting step to obtain individual chip scale packages.    
   
   
       8 . The method as claimed in  claim 7 , wherein the contact pads are formed at locations corresponding to the bonding pads on the semiconductor chip.  
   
   
       9 . The method as claimed in  claim 8 , wherein the anisotropic conductive adhesive layer is formed from an adhesive filled with a plurality of conductive particles, and the contact pads of the tape circuit are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles.  
   
   
       10 . The method as claimed in  claim 7 , wherein the tape circuit includes a plurality of conductive traces each having a first end portion formed at a location corresponding to one of the bonding pads on the semiconductor chip and a second end portion serving as the contact pad.  
   
   
       11 . The method as claimed in  claim 10 , wherein the anisotropic conductive adhesive layer is formed from an adhesive filled with a plurality of conductive particles, and the contact pads of the tape circuit are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles and the conductive traces.  
   
   
       12 . The method as claimed in  claim 7 , wherein the metal bumps are formed by placing a plurality of solder balls in the openings of the insulating layer and then conducting a reflowing step.  
   
   
       13 . The method as claimed in  claim 7 , wherein the metal bumps are formed by a solder paste stencil printing step and a reflowing step.  
   
   
       14 . A method for manufacturing chip scale packages at the wafer-level, the method comprising steps of: 
 providing a patterned circuit layer with a tape attached thereon, the patterned circuit layer including a plurality of contact pads on a lower surface thereof and a plurality of openings formed therein at locations corresponding to the contact pads such that each of the contact pads has a portion exposed from an upper surface of the patterned circuit layer through the corresponding opening;    providing a wafer including a plurality of semiconductor chips wherein each semiconductor chip has a plurality of bonding pads on an active surface thereof;    forming an anisotropic conductive adhesive layer onto the active surface of the wafer;    removing the tape from the patterned circuit layer and attaching the patterned circuit layer onto the wafer through the anisotropic conductive adhesive layer such that the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip;    forming a plurality of metal bumps in the openings of the patterned circuit layer and mounted to the exposed portions of the contact pads of the patterned circuit layer; and    conducting a cutting step to obtain individual chip scale packages.    
   
   
       15 . The method as claimed in  claim 14 , wherein the contact pads are formed at locations corresponding to the bonding pads on the semiconductor chip.  
   
   
       16 . The method as claimed in  claim 15 , wherein the anisotropic conductive adhesive layer is formed from an adhesive filled with a plurality of conductive particles, and the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles.  
   
   
       17 . The method as claimed in  claim 14 , wherein the patterned circuit layer includes a plurality of conductive traces each having a first end portion formed at a location corresponding to one of the bonding pads on the semiconductor chip and a second end portion serving as the contact pad.  
   
   
       18 . The method as claimed in  claim 17 , wherein the anisotropic conductive adhesive layer is formed from an adhesive filled with a plurality of conductive particles, and the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles and the conductive traces.  
   
   
       19 . The method as claimed in  claim 14 , wherein the metal bumps are formed by placing a plurality of solder balls in the openings of the patterned circuit layer and then conducting a reflowing step.  
   
   
       20 . The method as claimed in  claim 7 , wherein the metal bumps are formed by a solder paste stencil printing step and a reflowing step.  
   
   
       21 . A method for manufacturing chip scale packages at the wafer-level, comprising steps of: 
 providing a patterned circuit layer including a plurality of contact pads on the lower surface of the patterned circuit layer and a plurality of solder pads on the upper surface of the patterned circuit layer wherein the contact pads are electrically coupled to the corresponding solder pads;    providing a wafer including a plurality of semiconductor chips wherein each semiconductor chip has a plurality of bonding pads on an active surface thereof;    forming an anisotropic conductive adhesive layer having a plurality of conductive particles onto the active surface of the wafer;    attaching the patterned circuit layer onto the wafer through the anisotropic conductive adhesive layer such that the contact pads of the patterned circuit layer are electrically coupled to the corresponding bonding pads on the semiconductor chip only through the conductive particles;    mounting a plurality of metal bumps to the solder pads of the patterned circuit layer; and    conducting a cutting step to obtain individual chip scale packages.    
   
   
       22 . The method as claimed in  claim 21 , wherein the metal bumps are formed by a solder-ball placing step and a reflowing step.  
   
   
       23 . The method as claimed in  claim 21 , wherein the metal bumps are formed by a solder paste stencil printing step and a reflowing step.