Variable delay circuit

Abstract

A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay element coupled in parallel to the plural stages of first variable delay elements for delaying the reference clock signal, a phase comparator for comparing the phase of the reference clock signal delayed by the plural stages of first variable delay elements with the phase of the reference clock signal delayed by the second variable delay element, and a delay amount control unit for controlling the delay amount of each of the plural stages of first variable delay elements based on the comparison result of the phase comparator in order that the phase of the reference clock signal delayed by the plural stages of first variable delay elements is substantially the same as the phase of the reference clock signal delayed by the second variable delay element after predetermined cycles.

1 .- 7 . (canceled)  
   
   
       8 . A timing comparator comprising: 
 a dynamic D flip-flop circuit for latching and outputting a data signal with parasitic capacitance thereof based on a clock signal;    a D flip-flop circuit for latching and outputting the data signal outputted by said dynamic D flip-flop circuit based on a delayed clock signal; and    a buffer for delaying the clock signal received by the dynamic D flip-flop circuit by a predetermined time and supplying the delayed clock signal to the D flip-flop circuit.    
   
   
       9 . The timing comparator as claimed in claim  1 , wherein the D flip-flop circuit comprises a positive feed-back circuit and the D flip-flop circuit latches the data signal using the positive feed-back circuit.  
   
   
       10 . The timing comparator as claimed in claim  2 , wherein the predetermined time by which the buffer delays the clock signal is greater than a set-up time of the D flip-flop circuit.