Stacked package for electronic elements

Abstract

A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

1 . A stacked package for electronic elements, comprising: 
 a substrate, having a supporting surface, wherein a plurality of stud bumps are formed on the supporting surface by a stud bump process and directly contact the supporting surface; and    an electronic element, having a plurality of vias corresponding to the stud bumps, wherein the vias are respectively aligned with the stud bumps to securely mount the electronic element on the substrate.    
   
   
       2 . The stacked package for electronic elements of  claim 1 , wherein the material of the stud bumps is a conductive metal.  
   
   
       3 . The stacked package for electronic elements of  claim 1 , wherein the material of the stud bumps is gold, copper or aluminum.  
   
   
       4 . The stacked package for electronic elements of  claim 1 , wherein the element is a silicon chip, a GaAs chip, an InP chip or an epitaxily-grown chip.  
   
   
       5 . The stacked package for electronic elements of  claim 1 , wherein the substrate is an organic substrate, a ceramic substrate, a glass substrate, a silicon substrate or a GaAs substrate.  
   
   
       6 . The stacked package for electronic elements of  claim 1 , wherein each of the stud bumps has a bottom wider than a width of the corresponding via.  
   
   
       7 . The stacked package for electronic elements of  claim 1 , wherein each of the stud bumps protrudes from a top surface of the electronic element.