Resistor with reduced leakage

Abstract

A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.

1 . A resistor comprising: 
 a semiconductor layer;    a body region formed in a portion of the semiconductor layer, the body region being doped to a first conductivity type and having a first resistivity;    a first contact region formed in the semiconductor layer adjacent the body region, the first contact region being doped to the first conductivity type;    a second contact region formed in the semiconductor layer spaced from the first contact region by the body region, the second contact region being doped to the first conductivity type;    a dielectric layer overlying the body region, said dielectric comprising a material with a relative permittivity greater than about  8 ; and    a conductive electrode overlying said dielectric.    
   
   
       2 . The resistor of  claim 1  further comprising an insulator layer underlying the semiconductor layer.  
   
   
       3 . The resistor of  claim 1  wherein the electrode has a width larger than about 1 micron.  
   
   
       4 . The resistor of  claim 1  wherein the electrode has a length larger than about 1 micron.  
   
   
       5 . The resistor of  claim 1  further comprising spacers formed on sides of the electrode.  
   
   
       6 . A silicon-on-insulator resistor comprising: 
 a silicon layer overlying an insulator layer;    a body region formed in a portion of the silicon layer;    a dielectric layer overlying the body region, said dielectric comprising a high permittivity dielectric layer;    a conductive top electrode overlying said dielectric layer; and    a pair of doped regions formed in the silicon layer oppositely adjacent the body region, the pair of doped regions being doped to the same conductivity type as the body region.    
   
   
       7 . The resistor of  claim 6  wherein the high permittivity dielectric is selected from a group comprising of aluminum oxide, hafnium oxynitride, hafnium silicate, zirconium oxide, zirconium oxynitride, zirconium silicate, yttrium oxide, lanthanum oxide, cerium oxide, titanium oxide, and tantalum oxide, and combinations thereof.  
   
   
       8 . The resistor of  claim 6  wherein the permittivity dielectric layer comprises hafnium oxide.  
   
   
       9 . The resistor of  claim 6  wherein the silicon layer is a strained silicon layer.  
   
   
       10 . A silicon-on-insulator device comprising: 
 an active area comprising a silicon layer overlying an insulator layer;    a body region of a first conductivity type formed in a portion of the silicon layer;    a dielectric layer overlying the body region, said dielectric comprising a material selected from the group consisting of aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, zirconium oxide, zirconium oxynitride, zirconium silicate, yttrium oxide, lanthanum oxide, cerium oxide, titanium oxide, tantalum oxide, and combinations thereof;    a conductive top electrode overlying the dielectric layer; and    a pair of doped regions of the first conductivity type formed in the silicon layer oppositely adjacent the body region.    
   
   
       11 . The device of  claim 10  wherein the silicon layer has a thickness in the range of about 20 angstroms to about 400 angstroms.  
   
   
       12 . The device of  claim 10  and further comprising a second active area overlying the insulator layer, the second active area including a transistor formed therein.  
   
   
       13 . The device of  claim 12  wherein the transistor includes a gate dielectric formed of the same material as the dielectric layer overlying the body region.  
   
   
       14 . The device of  claim 12  wherein the transistor includes a gate dielectric formed of a different material as the dielectric layer overlying the body region.  
   
   
       15 . The device of  claim 12  wherein the transistor includes a gate electrode formed of the same material as the top electrode.  
   
   
       16 . A silicon-on-insulator device comprising: 
 a substrate;    an insulator layer overlying the substrate;    an active area formed in a silicon layer overlying the insulator layer;    a body region of a first conductivity type formed in a portion of the silicon layer;    an interfacial layer overlying and abutting the body region;    a high-k dielectric layer overlying the interfacial layer, the high-k dielectric layer comprising a material having a relative permittivity greater than about 8;    a conductive top electrode overlying the high-k dielectric layer; and    a pair of doped regions of the first conductivity type formed in the active area oppositely adjacent the body region.    
   
   
       17 . The device of  claim 16  and further comprising a second active area overlying the insulator layer, the second active area including a transistor formed therein.  
   
   
       18 . An electrostatic discharge protection circuit comprising: 
 an I/O pad;    a circuit that is to be protected;    a diode coupled between the I/O pad and a reference voltage node;    a resistor coupled between the I/O pad and the circuit, the resistor including a body region, a first contact region adjacent the body region to electrically couple the body region to the I/O pad, a second contact region adjacent the body region to electrically couple the body region to the circuit, a dielectric layer having a relative permittivity greater than about 8 overlying the body region, and an electrode overlying the dielectric layer.    
   
   
       19 . The circuit of  claim 18  wherein the diode comprises: 
 a diode body region;    a diode dielectric having a relative permittivity greater than about 8 overlying the diode body region;    a diode electrode overlying the diode dielectric; and    a p-doped region and an n-doped region oppositely adjacent to the diode body region.    
   
   
       20 . The circuit of  claim 19  wherein the p-doped region of the diode is electrically coupled to the I/O pad and the n-doped region of the diode is electrically coupled to the reference voltage node.  
   
   
       21 . The circuit of  claim 19  wherein the n-doped region of the diode is electrically coupled to the I/O pad and the p-doped region of the diode is electrically coupled to the reference voltage node.  
   
   
       22 . The circuit of  claim 18  and further comprising a second diode coupled between the I/O pad and a second reference voltage node.  
   
   
       23 . The circuit of  claim 22  wherein the second diode comprises: 
 a diode body region;    a diode dielectric having a relative permittivity greater than about 8 overlying the diode body region;    a diode electrode overlying the diode dielectric; and    a p-doped region and an n-doped region oppositely adjacent to the diode body region.    
   
   
       24 . The circuit of  claim 22  and further comprising: 
 a second circuit; and    a second resistor coupled between the second circuit and the I/O pad, the second resistor comprising a body region, a first contact region adjacent the body region to electrically couple the body region to the I/O pad, a second contact region adjacent the body region to electrically couple the body region to the second circuit, a dielectric layer having a relative permittivity greater than about 8 overlying the body region, and an electrode overlying the dielectric layer.    
   
   
       25 . The circuit of  claim 24  wherein the circuit comprises an output circuit and wherein the second circuit comprises an input circuit.