Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel

Abstract

A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

1 . A method of fabricating a semiconductor device, comprising: 
 forming a plurality of gate structures over a substrate;    forming a source region and a drain region in the substrate and adjacent to sidewalls of each of the gate structures;    forming a self-aligned salicide block (SAB) layer covering the gate structures and a surface of the substrate;    performing an anneal process, during the anneal process the SAB layer creating a tension stress so that the substrate under the gate structures is subjected to the tension stress;    removing a portion of the SAB layer to expose a portion of the gate structure and a portion of the surface of the substrate; and    performing a self-aligned salicide process.    
   
   
       2 . The method of fabricating the semiconductor device of  claim 1 , wherein the SAB layer comprises a material that creates the tension stress while being heated.  
   
   
       3 . The method of fabricating the semiconductor device of  claim 2 , wherein the material is silicon oxide or silicon nitride.  
   
   
       4 . The method of fabricating the semiconductor device of  claim 1 , wherein a thickness of the SAB layer is from about 500 Å to about 5000 Å.  
   
   
       5 . The method of fabricating the semiconductor device of  claim 1 , wherein the step of forming the source region and the drain region in the substrate and adjacent to the sidewalls of each of the gate structures comprises performing an ion implantation process.  
   
   
       6 . The method of fabricating the semiconductor device of  claim 1 , wherein the anneal process comprises a rapid thermal anneal (RTA) process.  
   
   
       7 . The method of fabricating the semiconductor device of  claim 1 , wherein the step of forming the self-aligned salicide comprises: 
 forming a metal layer over the substrate, covering a reserved SAB layer, the exposed portion of the gate structure, and the exposed portion of the surface of the substrate;    performing a thermal process so that a portion of the metal layer reacts to form a salicide layer; and    removing the metal layer that does not react.    
   
   
       8 . A method of adjusting a lattice distance of a device channel, comprising: 
 providing a substrate, a device formed over the substrate, the device at least comprising a gate structure and a channel region;    forming a lattice adjusting layer covering the device; and    performing a thermal process, during the thermal process the lattice adjusting layer creates a tension stress so that the tension stress changes a lattice distance of the channel region.    
   
   
       9 . The method of adjusting the lattice distance of the device channel of  claim 8 , wherein the lattice adjusting layer comprises a material that creates the tension stress while being heated.  
   
   
       10 . The method of adjusting the lattice distance of the device channel of  claim 9 , wherein the material is silicon oxide or silicon nitride.  
   
   
       11 . The method of adjusting the lattice distance of a device channel of  claim 8 , wherein a thickness of the lattice adjusting layer is from about 500 Å to about 5000 Å.  
   
   
       12 . The method of adjusting the lattice distance of the device channel of  claim 8 , wherein the anneal process comprises a rapid thermal anneal (RTA) process.