Polish method for semiconductor device planarization

Abstract

A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.

1 . A polish method for semiconductor device planarization, said method comprising: 
 providing a substrate having a first layer thereon and a second layer by a deposition process on said first layer, wherein said first layer and said second layer are not made of same material;    performing a first chemical mechanical polishing process to decrease a thickness difference value between a highest point and a lowest point of said second layer to a first predetermined thickness difference value without polishing said first layer; and    performing a second chemical mechanical polishing process to further decrease said first predetermined thickness difference value to a second predetermined thickness difference value and to expose said first layer, wherein said second chemical mechanical polishing process has a polish selectivity between said first layer and said second layer higher than a polish selectivity between said first layer and said second layer of said first chemical mechanical polishing process.    
   
   
       2 . The method according to  claim 1 , wherein said substrate comprises a silicon substrate having trenches therein.  
   
   
       3 . The method according to  claim 1 , wherein said first layer and said second layer comprise a silicon nitride layer and a silicon dioxide layer.  
   
   
       4 . The method according to  claim 1 , wherein said substrate has dual damascene trenches therein.  
   
   
       5 . The method according to  claim 1 , wherein said first layer and said second layer comprise a barrier metal layer and a metal layer.  
   
   
       6 . The method according to  claim 5 , wherein said barrier metal layer and said metal layer comprise a TiN layer and a copper layer.  
   
   
       7 . The method according to  claim 1 , wherein said first chemical mechanical polishing process is performed by using an oxide slurry and a polish pad.  
   
   
       8 . The method according to  claim 7 , wherein said oxide slurry comprises a silicon dioxide slurry.  
   
   
       9 . The method according to  claim 7 , wherein said oxide slurry comprises an alumina slurry.  
   
   
       10 . The method according to  claim 1 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad.  
   
   
       11 . The method according to  claim 1 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad and an additive.  
   
   
       12 . The method according to  claim 11 , wherein said additive comprises an oxide slurry, KOH solution and NH 4 OH solution.  
   
   
       13 . The method according to  claim 11 , wherein said additive comprises an oxide abrasive polish pad, an acid solution and an oxidizer solution.  
   
   
       14 . The method according to  claim 1 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad and a CeO 2  slurry.  
   
   
       15 . The method according to  claim 1 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad and an Al 2 O 3  slurry.  
   
   
       16 . A polish method for semiconductor device planarization, said method comprising: 
 providing a substrate having a first layer thereon and a second layer by a deposition process on said first layer, wherein said first layer and said second layer are not made of same material;    performing a first chemical mechanical polishing process by using an oxide slurry and a polish pad to decrease a thickness difference value between a highest point and a lowest point of said second layer to a first predetermined thickness difference value without polishing said first layer; and    performing a second chemical mechanical polishing process to further decrease said first predetermined thickness difference value to a second predetermined thickness difference value and to expose said first layer, wherein said second chemical mechanical polishing process has a polish selectivity between said first layer and said second layer higher than a polish selectivity between said first layer and said second layer of said first chemical mechanical polishing process.    
   
   
       17 . The method according to  claim 16 , wherein said substrate comprises a silicon substrate having trenches therein.  
   
   
       18 . The method according to  claim 16 , wherein said first layer and said second layer comprise a silicon nitride layer and a silicon dioxide layer.  
   
   
       19 . The method according to  claim 16 , wherein said substrate has dual damascene trenches therein.  
   
   
       20 . The method according to  claim 16 , wherein said first layer and said second layer comprise a barrier metal layer and a metal layer.  
   
   
       21 . The method according to  claim 20 , wherein said barrier metal layer and said metal layer comprise a TaN layer and a copper layer.  
   
   
       22 . The method according to  claim 16 , wherein said oxide slurry comprises a silicon dioxide slurry.  
   
   
       23 . The method according to  claim 16 , wherein said oxide slurry comprises an alumina slurry.  
   
   
       24 . The method according to  claim 16 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad.  
   
   
       25 . The method according to  claim 16 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad and an additive.  
   
   
       26 . The method according to  claim 25 , wherein said additive comprises an oxide slurry, KOH solution and NH 4 OH solution.  
   
   
       27 . The method according to  claim 25 , wherein said additive comprises an oxide abrasive polish pad, an acid solution and an oxidizer solution.  
   
   
       28 . The method according to  claim 16 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad and a CeO 2  slurry.  
   
   
       29 . The method according to  claim 14 , wherein said second chemical mechanical polishing process is performed by using a fix abrasive polish pad and an Al 2 O 3  slurry.  
   
   
       30 . A polish method for semiconductor device planarization, said method comprising: 
 providing a substrate having a first layer thereon and a second layer by a deposition process on said first layer, wherein said first layer and said second layer are not made of same material;    performing a first chemical mechanical polishing process by using an oxide slurry and a polish pad to decrease a thickness difference value between a highest point and a lowest point of said second layer to a first predetermined thickness difference value without polishing said first layer; and    performing a second chemical mechanical polishing process by using a fix abrasive polish pad to further decrease said first predetermined thickness difference value to a second predetermined thickness difference value and to expose said first layer.    
   
   
       31 . The method according to  claim 30 , wherein said substrate comprises a silicon substrate having trenches therein.  
   
   
       32 . The method according to  claim 30 , wherein said first layer and said second layer comprise a silicon nitride layer and a silicon dioxide layer.  
   
   
       33 . The method according to  claim 30 , wherein said substrate has dual damascene trenches therein.  
   
   
       34 . The method according to  claim 30 , wherein said first layer and said second layer comprise a barrier metal layer and a metal layer.  
   
   
       35 . The method according to  claim 34 , wherein said barrier metal layer and said metal layer comprise a tungsten layer and a copper layer.  
   
   
       36 . The method according to  claim 30 , wherein said oxide slurry comprises a silicon dioxide slurry.  
   
   
       37 . The method according to  claim 30 , wherein said oxide slurry comprises an alumina slurry.  
   
   
       38 . The method according to  claim 30 , wherein said second chemical mechanical polishing process is performed by using said fix abrasive polish pad and an additive.  
   
   
       39 . The method according to  claim 38 , wherein said additive comprises an oxide slurry, KOH solution and NH 4 OH solution.  
   
   
       40 . The method according to  claim 38 , wherein said additive comprises an oxide abrasive polish pad, an acid solution and an oxidizer solution.  
   
   
       41 . The method according to  claim 30 , wherein said second chemical mechanical polishing process is performed by using said fix abrasive polish pad and a CeO 2  slurry.  
   
   
       42 . The method according to  claim 30 , wherein said second chemical mechanical polishing process is performed by using said fix abrasive polish pad and an Al 2 O 3  slurry.