Chip package structure

Abstract

A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

1 . A chip package structure, comprising: 
 a carrier;    a chipset, set on and electrically connected to the carrier, wherein the chipset comprises a plurality of chips, at least one of the chips is bonded to the carrier or another chip using a flip-chip bonding technique so that a flip-chip bonding gap is created; and    an encapsulating material layer, completely filling the flip-chip bonding gap and covering the chipset and the carrier, wherein the encapsulating material layer within the flip-chip bonding gap has a first thickness and the encapsulating material layer on the chipset has a second thickness such that the second thickness is between 0.5˜2 times the first thickness.    
     
     
         2 . The chip package structure of  claim 1 , wherein maximum diameter of particles constituting the encapsulating material layer is smaller than 0.5 times the first thickness.  
     
     
         3 . The chip package structure of  claim 1 , wherein the chipset at least comprises: 
 a first chip, having a first active surface, wherein the first chip is attached to the carrier such that the first active surface is positioned away from the carrier; and    a second chip, having a second active surface with a plurality of bumps thereon, wherein the second active surface of the second chip is bonded and electrically connected to the first chip using a flip-chip bonding technique such that the bumps between the second chip and the first chip set a flip-chip bonding gap.    
     
     
         4 . The chip package structure of  claim 3 , wherein the chipset further comprises a plurality of conductive wires with ends electrically connected to the first chip and the carrier respectively.  
     
     
         5 . The chip package structure of  claim 1 , wherein the package further comprises a passive component attached and electrically connected to the carrier.  
     
     
         6 . The chip package structure of  claim 1 , wherein the package further comprises an array of solder balls attached to a surface of the carrier away from the chips.  
     
     
         7 . The chip package structure of  claim 1 , wherein the carrier is selected from a group consisting of a package substrate or a lead frame.