Air gap interconnect structure and method thereof

Abstract

Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of stakes having first openings therebetween, the plurality of stakes for providing mechanical supporting strength for the interconnect structure. A sacrificial layer is formed in the first openings and above the plurality of stakes. A hard mask layer is formed above the sacrificial layer. A light sensitive layer is formed over the hard mask layer and is thereafter patterned to define a pattern therein. The hard mask layer, the sacrificial layer, and the first barrier layer are etched according to the pattern in the light sensitive layer to form second openings. The second openings are filled with a conductive material to form metal lines. The sacrificial layer is thereafter removed to form air gaps. A second barrier layer is formed over the plurality of stakes and the metal lines, the second barrier layer thereby sealing the air gaps.

1 - 24 . (canceled)  
   
   
       25 . An interconnect structure, comprising: 
 a semiconductor substrate having a patterned barrier layer formed thereon;    a plurality of metal lines interposed between portions of the patterned barrier layer;    a plurality of dielectric dummy stakes interspersed between the plurality of metal lines for providing mechanical supporting strength for the interconnect structure;    air gaps formed between any one area of the plurality of dummy stakes and any one area of the plurality of metal lines;    a barrier layer sealing upper surfaces of the plurality of dummy stakes, the plurality of metal lines, and the air gaps.    
   
   
       26 . The interconnect structure of  claim 25 , wherein the substrate comprises a patterned single damascene vias of contacts in contact with the metal lines.  
   
   
       27 . The interconnect structure of  claim 25 , further comprising: 
 a dielectric layer formed above the barrier layer.    
   
   
       28 . A structure of air gaps between metal lines of a semiconductor device, comprising: 
 a semiconductor substrate having a patterned barrier layer formed thereon;    a plurality of metal lines interposed between portions of the patterned barrier layer;    a plurality of dielectric dummy stakes interspersed between the plurality of metal lines for providing mechanical supporting strength for the semiconductor device;    air gaps formed between any one area of the plurality of dummy stakes and the plurality of metal lines;    a barrier layer sealing upper surfaces of the plurality of dummy stakes, the plurality of metal lines, and the air gaps.    
   
   
       29 . The structure of  claim 28 , wherein the substrate comprises a patterned single damascene vias or contacts in contact with the metal lines.  
   
   
       30 . The structure of  claim 28 , further comprising: 
 a dielectric layer formed above the barrier layer.    
   
   
       31 . The interconnect structure of  claim 25 , wherein the dummy stakes have top surfaces coplanar with the top surfaces of the metal lines.  
   
   
       32 . The structure of  claim 28 , wherein the dummy stakes have top surfaces coplanar with the top surfaces of the metal lines.