Line level air gaps

Abstract

In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

1 . A process for fabricating a semiconductor device structure atop an FEOL semiconductor substrate, comprising: 
 a. depositing a first layer of permanent ultra-low K dielectric material atop the substrate, in which layer will be fabricated the first via level;    b. depositing a first layer of sacrificial material atop the first layer of permanent dielectric material, in which layer will be fabricated the first line level;    c. fabricating the first copper via and line levels by dual damascene processing and planarizing the first hard mask to expose the surface of the copper lines;    d. selectively depositing a thin protective cap on the exposed copper lines;    e. applying a blanket of permanent dielectric atop the wiring level; and    f. annealing the structure under vacuum in an inert atmosphere by gradually increasing the temperature to a level and for a time sufficient to decompose and remove the sacrificial material.    
   
   
       2 . The process recited in  claim 1 , including the step of applying a first gas impermeable etch stop layer between the first permanent ultra-low K dielectric material and the first sacrificial layer.  
   
   
       3 . The process recited in  claim 2 , wherein the step of applying a first gas impermeable etch stop comprises applying a first gas impermeable etch stop selected from the group consisting of SiO 2 , SiN, SiC, SiCH, and SiNCH.  
   
   
       4 . The process recited in  claim 1 , wherein the first layer of permanent ultra-low K dielectric material is selected from the group consisting of SiLK and porous SiLK, JSR, MSSQ and porous MSSQ.  
   
   
       5 . The process recited in  claim 1 , wherein the first layer of sacrificial material is selected from the group consisting of polystyrenes; polymethyl methacrylates; polynorbornenes; and polypropylene glycols  
   
   
       6 . The process recited in  claim 1 , wherein the first gas permeable hard mask is selected from the group consisting of HOSP and HOSP Best, JSR 5140, JSR 2021, SiCOH, polycarbonates and any combination thereof.  
   
   
       7 . The process recited in  claim 1 , wherein the cap is selected from the group consisting of CoWP, Ta, W, TaN, Ru, and any combination thereof.  
   
   
       8 . The process recited in  claim 1 , wherein the steps of a-g are repeated atop the annealed structure at step g as substrate until attaining the number of levels desired.  
   
   
       9 . Fabricating an initial subset for a semiconductor device structure, comprising atop an FEOL semiconductor substrate: 
 a. providing a gas impermeable etch stop level atop the substrate;    b. depositing a first sacrificial dielectric material atop the etch stop and a first permeable CMP hard mask atop the first sacrificial dielectric;    c. fabricating an opening through the hard mask and depositing therein a first copper line level for electrical communication with the FEOL substrate;    d. planarizing to expose the copper lines and make them even with the first hard mask, and applying thereover a first permanent, solid, partially cured ultra-low K dielectric material which is capable of developing porosities at processing temperature;    e. providing a first anneal to the structure under vacuum in an inert atmosphere by gradually increasing the temperature to a level and for a time sufficient to decompose and remove the sacrificial material from the first line level while also finally curing and creating porosities in the permanent ultra-low K dielectric material;    f. applying a second layer of sacrificial dielectric atop the first permanent ultra-low K dielectric material, and applying a second permeable hard mask thereover;    g. fabricating the first copper via and second copper line levels on the second hard mask by dual damascene processing and planarizing to expose the surface of the copper lines and make them even with the second permeable hard mask;    h. applying on the second permeable hard mask a second permanent, solid, partially cured ultra-low K dielectric material which is capable of developing porosities at processing temperature; and    i. providing a second anneal to the structure under vacuum in an inert atmosphere by gradually increasing the temperature to a level and for a time sufficient to decompose and remove the sacrificial material from the second line level while also finally curing and creating porosities in the second permanent ultra-low K dielectric material.    
   
   
       10 . The process recited in  claim 9 , wherein steps g-i are repeated as required.  
   
   
       11 . The process recited in  claim 10 , wherein the steps of applying permanent, solid, partially cured ultra-low K dielectric material which is capable of developing porosities at processing temperature comprises applying a material selected from the group consisting of SiLK, MSSQ, and SiCOH.