Interposers with alignment fences and semiconductor device assemblies including the interposers

Abstract

An interposer includes a fence that orients or aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. The fence may comprise a unitary structure or a plurality of mutually adhered regions.

1 . A semiconductor device assembly, comprising: 
 an interposer comprising: 
 an interposer substrate with a surface at which contact pads are exposed;  
 a fence comprising a plurality of adjacent, mutually adhered regions on the surface, the fence including at least one laterally recessed area and forming a receptacle at which the contact pads are exposed; and  
   a semiconductor device positioned adjacent to the surface, oriented by the fence, and including bond pads aligned with corresponding contact pads of the interposer.    
   
   
       2 . The semiconductor device assembly of  claim 1 , further comprising: conductive structures positioned between the bond pads and their corresponding contact pads.  
   
   
       3 . The semiconductor device assembly of  claim 1 , wherein the fence comprises photopolymer.  
   
   
       4 . The semiconductor device assembly of  claim 1 , wherein the interposer includes at least one protective layer covering at least a portion of the surface.  
   
   
       5 . The semiconductor device assembly of  claim 1 , wherein at least a portion of the fence extends over at least a portion of at least one peripheral edge of the interposer substrate.  
   
   
       6 . The semiconductor device assembly of  claim 1 , wherein the interposer further comprises conductive structures in communication with contact pads carried by an opposite surface of the interposer substrate.  
   
   
       7 . The semiconductor device assembly of  claim 1 , further comprising: 
 a substrate comprising contact pads positioned correspondingly to and in communication with second conductive structures in communication with corresponding bottom contact pads.    
   
   
       8 . The semiconductor device assembly of  claim 7 , wherein the substrate is a test substrate.  
   
   
       9 . The semiconductor device assembly of  claim 7 , wherein the substrate is a carrier substrate.  
   
   
       10 . The semiconductor device assembly of  claim 1 , wherein the contact pads are recessed below the surface of the interposer.  
   
   
       11 . The semiconductor device assembly of  claim 10 , wherein the interposer further includes at least one knife-edged spine protruding into a recess above each of the contact pads.  
   
   
       12 . The semiconductor device assembly of  claim 11 , wherein the at least one knife-edged spine is metallized.  
   
   
       13 . The semiconductor device assembly of  claim 12 , wherein metallization of the at least one knife-edged spine communicates with a corresponding one of the selected contact pads.  
   
   
       14 . The semiconductor device assembly of  claim 11 , wherein the at least one knife-edged spine is configured to pierce a conductive structure protruding from a bond pad of the semiconductor device.  
   
   
       15 . The semiconductor device assembly of  claim 1 , wherein the at least one laterally recessed region is positioned at a corner of the fence.  
   
   
       16 . The semiconductor device assembly of  claim 1 , wherein the at least one laterally recessed region is configured to facilitate rough alignment of the semiconductor device with the interposer substrate.  
   
   
       17 . The semiconductor device assembly of  claim 1 , comprising at least two laterally recessed regions located at opposite corners of the receptacle.  
   
   
       18 . An interposer for electrically connecting a semiconductor device to a substrate, comprising: 
 an interposer substrate with a top surface and a bottom surface;    a first array of contact pads exposed at the top surface and located correspondingly to conductive structures of the semiconductor device; and    a fence positioned on the top surface, the fence including at least one laterally recessed area in an interior periphery thereof; and    a receptacle formed by the fence, the first array of contact pads being exposed in the receptacle, the receptacle configured to receive the semiconductor device and the fence configured to align the semiconductor device with the interposer substrate.    
   
   
       19 . The interposer of  claim 18 , wherein the fence comprises at least one protective layer extending over at least a portion of at least one of the top surface and the bottom surface.  
   
   
       20 . The interposer of  claim 18 , wherein the fence extends over at least a portion of at least one peripheral edge of the interposer substrate.  
   
   
       21 . The interposer of  claim 18 , further comprising: 
 a second array of contact pads exposed at the bottom surface of the interposer substrate.    
   
   
       22 . The interposer of  claim 21 , wherein at least one contact pad of the second array communicates with a corresponding contact pad of the first array by way of a via extending at least partially through the interposer substrate.  
   
   
       23 . The interposer of  claim 21 , further comprising second conductive structures secured to selected ones of the contact pads of the second array.  
   
   
       24 . The interposer of  claim 18 , wherein the fence comprises a dielectric material.  
   
   
       25 . The interposer of  claim 24 , wherein the dielectric material comprises a photopolymer.  
   
   
       26 . The interposer of  claim 18 , wherein the receptacle comprises tapered walls configured to progressively guide a semiconductor device assembled with the interposer into alignment with the interposer substrate.  
   
   
       27 . The interposer of  claim 18 , wherein the at least one laterally recessed region is configured to facilitate rough alignment of a semiconductor device with the interposer substrate.  
   
   
       28 . The interposer of  claim 18 , wherein the fence includes at least two laterally recessed regions located at corners thereof.  
   
   
       29 . The interposer of  claim 18 , wherein selected contact pads of the first array are recessed below the top surface.  
   
   
       30 . The interposer of  claim 29 , wherein the interposer substrate further includes at least one knife-edged spine protruding into a recess above each of the selected contact pads, the at least one knife-edged spine being configured to pierce a conductive structure of a semiconductor device upon assembly with the interposer.  
   
   
       31 . The interposer of  claim 30 , wherein the at least one knife-edged spine is metallized.  
   
   
       32 . The interposer of  claim 31 , wherein metallization of the at least one knife-edged spine communicates with a corresponding one of the selected contact pads.  
   
   
       33 . A semiconductor device assembly, comprising: 
 an interposer comprising: 
 an interposer substrate with 
 a top surface at which top contact pads are exposed; and  
 a bottom surface opposite the top surface;  
 
 a fence comprising at least one laterally recessed area in an interior peripheral edge thereof; and  
   a receptacle within the fence, the top contact pads being exposed within the receptacle; and    a semiconductor device disposed at least partially in the receptacle, the semiconductor device comprising conductive elements positioned in alignment with the top contact pads and in communication therewith.    
   
   
       34 . The semiconductor device assembly of  claim 33 , wherein the interposer comprises bottom contact pads exposed at the bottom surface of the interposer substrate.  
   
   
       35 . The semiconductor device assembly of  claim 34 , wherein at least one top contact pad communicates with at least one bottom contact pad by way of a via extending at least partially through the interposer substrate.  
   
   
       36 . The semiconductor device assembly of  claim 34 , further comprising: 
 bottom conductive structures in communication with corresponding bottom contact pads.    
   
   
       37 . The semiconductor device assembly of  claim 34 , further comprising: 
 a substrate comprising contact pads positioned correspondingly to and in communication with conductive structures in communication with corresponding bottom contact pads.    
   
   
       38 . The semiconductor device assembly of  claim 37 , wherein the substrate is a test substrate.  
   
   
       39 . The semiconductor device assembly of  claim 37 , wherein the substrate is a carrier substrate.  
   
   
       40 . The semiconductor device assembly of  claim 33 , wherein the at least one laterally recessed region is configured to facilitate rough alignment of the semiconductor device with the interposer substrate.  
   
   
       41 . The semiconductor device assembly of  claim 33 , comprising at least two laterally recessed regions located at opposite corners of the fence.