Fan out type wafer level package structure and method of the same

Abstract

To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.

1 . A process of fan out type wafer level package, comprising the steps of: 
 adhering a first plurality of dies to an isolating base;    forming a first material layer on said isolating base to fill in a space among said first plurality of dies on said isolating base;    curing said first material layer;    forming a second material layer on said first material layer and said first plurality of dies;    etching a partial region of said second material layer on first pads of said first plurality of dies to form first openings;    curing said second material layer;    forming first contact conductive layer on said first openings to electrically couple with said first pads, respectively;    forming a first photo resist layer on said second material layer and said first contact conductive layer;    removing a partial region of said first photo resist layer to form a first fan out pattern and expose said first contact conductive layer;    forming first conductive lines on said first fan out pattern and said first conductive lines being coupled with said first contact conductive layer, respectively;    removing remaining said first photo resist layer;    forming a first isolation layer on said first conductive lines and said second material layer;    removing a partial region of said first isolation layer on said first conductive lines to forming second openings;    curing said first isolation layer; and    welding solder balls on said second openings.    
     
     
         2 . The process in  claim 1 , wherein surfaces of said first material layer and said first plurality of dies are at same level.  
     
     
         3 . The process in  claim 1 , further comprising a step of sawing said base to isolate said first plurality of dies after the step of said welding solder balls.  
     
     
         4 . The process in  claim 1 , further comprising a step of adhering a plurality of first passive components to said isolating base among said first plurality of dies onto an isolating base before the step of forming said first material layer.  
     
     
         5 . The process in  claim 1 , wherein said first plurality of dies comprises at least two types of dies.  
     
     
         6 . The process in  claim 1 , wherein said first plurality of dies is formed by sawing a processed silicon wafer.  
     
     
         7 . The process in  claim 4 , wherein said processed silicon wafer is back lapped to get a thickness of said processed silicon wafer around 50-300 μm.  
     
     
         8 . The process in  claim 1 , wherein materials of said first material layer and said second material layer comprise UV curing type material, heat curing type material, and the combination thereof.  
     
     
         9 . The process in  claim 1 , further comprising a step of cleaning each surface of said first pads by using plasma etching after the step of etching a partial region of said second material layer.  
     
     
         10 . The process in  claim 1 , further comprising a step of forming an epoxy layer on back surface of the base.  
     
     
         11 . The process in  claim 1 , wherein said first contact conductive layer comprises Ti, Cu, and the combination thereof.  
     
     
         12 . The process in  claim 1 , wherein said first conductive lines comprise Ni, Cu, Au, and the combination thereof.  
     
     
         13 . The process in  claim 1 , wherein said isolation layer comprises epoxy, resin, and the combination thereof.  
     
     
         14 . The process in  claim 1 , wherein a material of said isolating base is glass, silicon, ceramic, or crystal material.  
     
     
         15 . The process in  claim 1 , wherein said isolating base is a round type or a rectangular type.  
     
     
         16 . The process in  claim 1 , wherein said first contact conductive layer and said first conductive lines are formed by a forming method comprising physical method, chemical method, and the combination thereof.  
     
     
         17 . The process in  claim 16 , wherein said forming method comprising CVD, PVD, sputter, and electroplating.  
     
     
         18 . The process in claim l, wherein the step of welding said solder balls comprises placing said solder balls on said second openings by a screen printing method and joining said solder balls together with surfaces of said first conductive lines by a IR reflow method.  
     
     
         19 . The process in  claim 1  further comprising further steps before the step of removing a partial region of said first isolation layer, said further steps being: 
 adhering a second plurality of dies to said first isolation layer in the vertical direction of said first plurality of dies;    forming a third material layer on said first isolation layer to fill in a space among said second plurality of dies on said first isolation layer;    curing said third material layer;    forming a fourth material layer on said third material layer and said second plurality of dies;    etching a partial region of said fourth material layer on second pads of said second plurality of dies to form third openings;    curing said fourth material layer;    forming second contact conductive layer on said third openings to electrically coupling with said second pads, respectively;    removing a partial region of said fourth material layer, said third material layer, and said second material layer on said first conductive lines to forming second openings;    filling up said openings with conductive material and surfaces of said conductive material and said fourth material layer are at same level;    forming a second photo resist layer on said fourth material layer, said conductive material, and said second contact conductive layer;    removing a partial region of said second photo resist layer to form a second fan out pattern and expose said second contact conductive layer and said conductive material;    forming second conductive lines on said second fan out pattern and said second conductive lines being coupled with corresponding said second contact conductive layer and corresponding said conductive material;    removing remaining said second photo resist layer;    forming a second isolation layer on said second conductive lines and said fourth material layer;    removing a partial region of said second isolation layer on said second conductive lines to forming third openings;    curing said second isolation layer; and    welding solder balls on said third openings.    
     
     
         20 . The process in  claim 19 , wherein surfaces of said third material layer and said second plurality of dies are at same level  
     
     
         21 . The process in  claim 19 , further comprising a step of sawing said base to isolate packaged dies having one of said first plurality of dies and one of said second plurality of dies.  
     
     
         22 . The process in  claim 19 , further comprising a step of adhering a second plurality of first passive components to said isolating base among said second plurality of dies onto said first isolation layer before the step of forming said third material layer.  
     
     
         23 . The process in  claim 19 , wherein said second plurality of dies comprises at least two types of dies.  
     
     
         24 . The process in  claim 19 , wherein materials of said third material layer and said fourth material layer comprises UV curing type material, heat curing type material, and the combination thereof.  
     
     
         25 . The process in  claim 19 , further comprising a step of cleaning each surface of said second pads by using plasma etching after the step of etching a partial region of said fourth material layer.  
     
     
         26 . The process in  claim 19 , wherein said second contact conductive layer comprises Ti, Cu, and the combination thereof.  
     
     
         27 . The process in  claim 19 , wherein said second conductive lines comprises Ni, Cu, Au, and the combination thereof.  
     
     
         28 . The process in  claim 19 , wherein said second contact conductive layer and said second conductive lines are formed by a forming method comprising physical method, chemical method, and the combination thereof.  
     
     
         29 . The process in  claim 19 , wherein the step of welding said solder balls comprises placing said solder balls on said third openings by a screen printing method and joining said solder balls together with surfaces of said second conductive lines by a IR reflow method.