Mobility enhancement by strained channel CMOSFET with single workfunction metal-gate and fabrication method thereof

Abstract

The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

1 . A method of forming a complementary MOSFET consisting of a PMOSFET and an NMOSFET, comprising: 
 providing a semiconductor substrate with regions of a PMOSFET and an NMOSFET;    forming a compressively strained film overlying the PMOSFET channel;    forming gate dielectric layers on the NMOSFET region and the compressively strained film, respectively;    forming gate electrodes on the gate dielectric layers; and    forming a cap layer overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.    
   
   
       2 . The method as claimed in  claim 1 , wherein formation of the compressively strained film overlying the PMOSFET region comprises: 
 forming an amorphous layer overlying the semiconductor substrate, including the PMOSFET and the NMOSFET regions;    removing the amorphous layer overlying the PMOSFET region; and    forming the compressively strained film overlying the PMOSFET region by selective epitaxy.    
   
   
       3 . The method as claimed in  claim 2 , further comprising removing the amorphous layer overlying the NMOSFET.  
   
   
       4 . The method as claimed in  claim 2 , wherein the amorphous layer comprises an oxide layer.  
   
   
       5 . The method as claimed in  claim 1 , wherein the semiconductor substrate comprises Si.  
   
   
       6 . The method as claimed in  claim 1 , wherein the compressively strained film comprises a SiGe epitaxial layer.  
   
   
       7 . The method as claimed in  claim 6 , wherein the SiGe epitaxial layer has a Ge concentration from 0.1% to 100%.  
   
   
       8 . The method as claimed in  claim 6 , wherein the SiGe epitaxial layer has a thickness from 1 nm to 500 nm.  
   
   
       9 . The method as claimed in  claim 1 , wherein the PMOSFET region is a n-type well, and the NMOSFET region is a p-type well.  
   
   
       10 . The method as claimed in  claim 1 , wherein the gate dielectric layers have a dielectric constant higher than that of silicon dioxide.  
   
   
       11 . The method as claimed in  claim 1 , wherein the gate dielectric layers comprise ZrO 2 , HfO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , La 2 O 3 , SiON.  
   
   
       12 . The method as claimed in  claim 1 , wherein the gate electrodes have a Fermi level corresponding to a mid-gap of the semiconductor substrate.  
   
   
       13 . The method as claimed in  claim 12 , wherein the gate electrodes comprise poly-Si, poly-SiGe, or metals.  
   
   
       14 . The method as claimed in  claim 13 , wherein the metals comprise TiN, Ti, TaN, Ta, or W.  
   
   
       15 . The methods as claimed in  claim 1 , wherein the cap layer comprises SiN.  
   
   
       16 . The method as claimed in  claim 15 , wherein the cap layer has a thickness from 1 nm to 1 μm.  
   
   
       17 . The method as claimed in  claim 1 , wherein the cap layer is further formed overlying the PMOSFET region, and further doped with Ge ions at positions overlying the PMOSFET, such that the channel of the PMOSFET is substantially free of a tensile stress.  
   
   
       18 . The method as claimed in  claim 1 , wherein the cap layer is further formed overlying the PMOSFET region, and the method further comprises removing the cap layer formed overlying the PMOSFET region.  
   
   
       19 . A CMOSFET, comprising: 
 a semiconductor substrate with an isolation region for defining regions of a PMOSFET and an NMOSFET;    a compressively strained film overlying the PMOSFET region as a channel of the PMOSFET;    gate dielectric layers on the NMOSFET region and the compressively strained film, respectively;    gate electrodes on the gate dielectric layers; and    a cap layer overlying the NMOSFET region for producing a local tensile stress on a channel of the NMOSFET.    
   
   
       20 . The CMOSFET as claimed in  claim 19 , wherein the semiconductor substrate comprises Si.  
   
   
       21 . The CMOSFET as claimed in  claim 19 , wherein the compressively strained film comprises a SiGe epitaxial layer.  
   
   
       22 . The CMOSFET as claimed in  claim 21 , wherein the compressively strained film has a Ge concentration from 0.1% to 100%.  
   
   
       23 . The CMOSFET as claimed in  claim 21 , wherein the SiGe epitaxial layer has a thickness from 1 nm to 500 nm.  
   
   
       24 . The CMOSFET as claimed in  claim 19 , wherein the PMOSFET region is a n-type well and the NMOSFET region is a p-type well.  
   
   
       25 . The CMOSFET as claimed in  claim 19 , wherein the gate dielectric layers have a dielectric constant higher than that of silicon dioxide.  
   
   
       26 . The CMOSFET as claimed in  claim 19 , wherein the gate dielectric layers comprise ZrO 2 , HfO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , La 2 O 3 , SiON.  
   
   
       27 . The CMOSFET as claimed in  claim 19 , wherein the gate electrodes have a Fermi level corresponding to a mid-gap of the semiconductor substrate.  
   
   
       28 . The CMOSFET as claimed in  claim 27 , wherein the gate electrodes comprise poly-Si, poly-SiGe, or metals.  
   
   
       29 . The CMOSFET as claimed in  claim 28 , wherein the metals comprise TiN, Ti, TaN, Ta, or W.  
   
   
       30 . The CMOSFET as claimed in  claim 19 , wherein the cap layer comprises SiN.  
   
   
       31 . The CMOSFET as claimed in  claim 19 , wherein the cap layer has a thickness from 1 nm to 1 μm.  
   
   
       32 . The CMOSFET as claimed in  claim 19 , wherein the cap layer is further formed overlying the PMOSFET region, and further doped with Ge ions at positions overlying the PMOSFET region, such that the channel of the PMOSFET is substantially free of a tensile stress.