Semiconductor device and method for fabricating the same

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

1 . A semiconductor device, comprising: 
 a plurality of capacitor plugs formed within a predetermined interval interleaved between two bit lines and midpoints of capacitor plugs are located at inter-section points of X axis virtual line and Y axis virtual line, wherein the X axis virtual lines are parallel with the bit lines and the Y axis virtual lines are perpendicular to the X axis virtual lines; and    a plurality of lower electrodes of capacitors formed within a predetermined interval to be respectively connected with the capacitor plugs in one to one correspondence.    each lower electrode being octagonally or circularly shaped.    
   
   
       2 . The semiconductor device as recited in  claim 1 , wherein a lower electrode and neighbored lower electrode disposed along a direction of Y virtual axis line are formed not to have overlapped area, if one of lower electrode is moved to same X virtual axis line as the other lower electrode.  
   
   
       3 . The semiconductor device as recited in  claim 1 , wherein the lower electrode and neighbored lower electrode disposed along a direction of Y virtual axis are not on the same Y virtual axis.  
   
   
       4 . The semiconductor device as recited in  claim 1 , wherein the midpoints of the lower electrode and the neighbored lower electrode are not disposed along the same Y virtual axis.  
   
   
       5 . The semiconductor device as recited in  claim 1 , wherein a ratio of a major axis to a minor axis of the upper plane of the lower electrodes ranges from about 1 to 1 to about 2 to 1.  
   
   
       6 . The semiconductor device as recited in  claim 1 , wherein an area of an upper plane of the lower electrode is practically identical to that of an lower plane of the lower electrode in view of a three-dimensional structure and the lower electrode features a octagonal or a circular cylinder structure having a lateral plane connecting the upper plane with the lower plane, wherein the lateral plane is substantially vertical to the upper plane and lower plane respectively.  
   
   
       7 . A method for fabricating a semiconductor device, comprising: 
 a) forming a plurality of capacitor plugs within a predetermined interval interleaved between two bit lines by arranging midpoints of capacitor plugs located at inter-section points of X axis virtual line and Y axis virtual line, wherein the X axis virtual lines are parallel with the bit lines and the Y axis virtual lines are perpendicular to the X axis virtual lines; and    b) forming a plurality of lower electrodes of capacitors within a predetermined interval to be respectively connected with the capacitor plugs in one to one correspondence, each lower electrode being octagonally or circularly shaped.    
   
   
       8 . The method as recited in  claim 7 , wherein an area of an upper plane of the lower electrode is practically identical to that of an lower plane of the lower electrode and the lower electrode has an octagonal or circular cylinder structure which has a lateral plane connecting the upper plane with the lower plane and practically vertical to the upper plane and lower plane.