Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.

1 . A semiconductor device comprising: 
 an interlayer insulating film having a first side wall and a second side wall,    said first side wall defining a through hole and said second side wall defining a trench;    a via contact formed in said through hole; and    a wiring formed in said trench and electrically connected to said via contact,    wherein said first side wall is higher in oxygen concentration than said second side wall.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein said first side wall is lower in hydrogen concentration than said second side wall.  
   
   
       3 . A semiconductor device comprising: 
 an interlayer insulating film having a first side wall and a second side wall,    said first side wall defining a through hole and said second side wall defining a trench;    a via contact formed in said through hole; and    a wiring formed in said trench and electrically connected to said via contact,    wherein said first side wall is higher in density than said second side wall.    
   
   
       4 . A semiconductor device comprising: 
 an interlayer insulating film having a first side wall and a second side wall,    said first side wall defining a through hole and said second side wall defining a trench;    a via contact formed in said through hole; and    a wiring formed in said trench and electrically connected to said via contact,    wherein said first side wall is higher in a ratio of Si—O bond than said second side wall.    
   
   
       5 . The semiconductor device according to  claim 4 , wherein said first side wall is lower in a ration of Si—H bond than said second side wall.  
   
   
       6 . The semiconductor device according to  claim 4 , wherein said via contact and said wiring are a dual damascene structure.  
   
   
       7 . The semiconductor device according to  claim 4 , wherein said interlayer insulating film has a first insulating layer and a second insulating layer, said first insulating layer has said first side wall and said second insulating layer has said second side wall.  
   
   
       8 . The semiconductor device according to  claim 7 , further comprising an etch stop film intervening between said first insulating layer and said second insulating layer.  
   
   
       9 . The semiconductor device according to  claim 4 , further comprising a semiconductor substrate, wherein said via contact is located between said wiring and said semiconductor substrate.  
   
   
       10 . The semiconductor device according to  claim 4 , wherein said via contact and said wiring are made of Cu.  
   
   
       11 . The semiconductor device according to  claim 4 , wherein said trench is wider in aperture than said through hole.  
   
   
       12 . The semiconductor device according to  claim 1 , wherein said via contact and said wiring are dual damascene structure.  
   
   
       13 . The semiconductor device according to  claim 3 , wherein said via contact and said wiring are dual damascene structure.  
   
   
       14 . The semiconductor device according to  claim 1 , wherein said interlayer insulating film has a first insulating layer and a second insulating layer, said first insulating layer has said first side wall and said second insulating layer has said second side wall.  
   
   
       15 . The semiconductor device according to  claim 3 , wherein said interlayer insulating film has a first insulating layer and a second insulating layer, said first insulating layer has said first side wall and said second insulating layer has said second side wall.  
   
   
       16 . The semiconductor device according to  claim 1 , further comprising a semiconductor substrate, wherein said via contact is located between said wiring and said semiconductor substrate.  
   
   
       17 . The semiconductor device according to  claim 3 , further comprising a semiconductor substrate, wherein said via contact is located between said wiring and said semiconductor substrate.  
   
   
       18 . The semiconductor device according to  claim 1 , wherein said via contact and said wiring are made of Cu.  
   
   
       19 . The semiconductor device according to  claim 3 , wherein said via contact and said wiring are made of Cu.  
   
   
       20 . The semiconductor device according to  claim 1 , wherein said trench is wider in aperture than said through hole.  
   
   
       21 . The semiconductor device according to  claim 3 , wherein said trench is wider in aperture than said through hole.