Ultrathin leadframe BGA circuit package

Abstract

A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while supporting leadframe fingers are positioned below the reference plane. Jumper wires are wirebonded between terminals on the die and the bond pads to form a package subassembly. The subassembly is encapsulated and then background to remove the leadframe fingers and surrounding frame. The bond pads which remain embedded in the encapsulation material are exposed on the lower surface of the package for connection to further conductors.

1 . A method for forming an integrated circuit package, comprising: 
 forming a leadframe having at least one bond pad and a support member coupled to the bond pad and extending away from the bond pad, the bond pad and the support member formed from a conductive material having a lower surface that defines a reference plane;    positioning a portion of the support member extending away from the bond pad on a first side of the reference plane;    positioning a die adjacent the bond pad with a lower surface of the die positioned on an opposing second side of the reference plane;    coupling a terminal on the die to the bond pad;    encapsulating the die, the bond pad and the support member in an interstitial material; and    removing at least a portion of the interstitial material on the first side of the reference plane to expose a lower face of the bond pad.    
   
   
       2 . The method of  claim 1 , wherein positioning a portion of the support member extending away from the bond pad on a first side of the reference plane further comprises deforming the leadframe to position the portion of the support member onto the first side of the reference plane.  
   
   
       3 . The method of  claim 2 , wherein a portion of a length of the support members is fixably adhered to a support surface.  
   
   
       4 . The method of  claim 1 , wherein positioning a portion of the support member extending away from the bond pad on a first side of the reference plane further comprises selectively etching portions of the leadframe to reduce a dimension of the support member to position an upper surface of the support member on the first side of the reference plane.  
   
   
       5 . The method of  claim 1 , wherein positioning a die further comprises coupling the die to a die pad having a lower surface positioned on the second side of the reference plane.  
   
   
       6 . The method of  claim 1 , wherein coupling a terminal on the die to the bond pad further comprises wirebonding a jumper wire between the terminal and the bond pad.  
   
   
       7 . The method of  claim 1 , wherein removing at least a portion of the interstitial material further comprises mechanically grinding the interstitial material.  
   
   
       8 . A method for forming an integrated circuit package, comprising: 
 forming a leadframe having a frame member enclosing a space for receiving a semiconductor integrated circuit die, the frame member having at least one finger coupled to the frame member and extending into the space and having a bond pad configured to be coupled to the die;    positioning a die in the space and coupling the bond pad to a terminal on the die;    offsetting a surface of the frame member and at least a portion of a length of the finger to be positioned below a lower one of the die and the bond pad;    providing an interstitial material that encapsulates the leadframe and the die; and    removing a portion of the interstitial material to define a package to expose the bond pad.    
   
   
       9 . The method of  claim 8 , wherein the leadframe further comprises a die pad; and further wherein positioning a die comprises bonding the die to the die pad.  
   
   
       10 . The method of  claim 9 , wherein bonding the die to the die pad further comprises fixably adhering a surface of the die to the die pad.  
   
   
       11 . A method comprising: 
 forming a leadframe having at least one finger coupled to a frame portion that encloses the finger, an end portion of the finger supporting a bond pad;    positioning at least a portion of the finger below a reference plane defined by a lower surface of the bond pad;    coupling a die to a die pad approximately aligned with the reference plane;    fixably adhering a portion of the leadframe to a support surface;    coupling a terminal on the die to the bond pad;    encapsulating the die, the die pad, the bond pad and the at least a portion of the finger by providing an interstitial material; and    removing a portion of the interstitial material below the reference plane to expose a surface of the bond pad.    
   
   
       12 . The method of  claim 11 , wherein coupling a terminal on the die to the bond pad further comprises wirebonding a conductor between the terminal and the bond pad.  
   
   
       13 . The method of  claim 11 , wherein positioning at least a portion of the finger below a reference plane further comprises deforming the leadframe to move the portion of the finger below the reference plane.  
   
   
       14 . The method of  claim 11 , wherein positioning at least a portion of the finger below a reference plane further comprises etching the portion of the finger to position a surface of the finger below the reference plane.  
   
   
       15 . A method, comprising: 
 forming a leadframe having a frame portion with at least one finger extending inwardly from the frame portion, the finger supporting a bond pad;    placing a portion of the finger below a reference plane defined by a surface of the bond pad;    mounting a die on a die pad proximate to the reference plane;    coupling a terminal on the die to the bond pad; and    encapsulating the die, the die pad, the at least one bond pad and the portion of the finger with an encapsulating material to form an integrated circuit package; and    removing encapsulating material below the reference plane to expose a surface of the bond pad.    
   
   
       16 . The method of  claim 15 , wherein removing encapsulating material comprises grinding the integrated circuit package.  
   
   
       17 . The method of  claim 16 , further comprising grinding a portion of the finger.  
   
   
       18 . The method of  claim 14 , wherein removing encapsulating material further comprises singulating the integrated circuit package.  
   
   
       19 . A method, comprising 
 forming a leadframe having an at least partially surrounding frame portion with at least one finger extending inwardly from the frame portion, a portion of the finger supporting a bond pad;    placing the portion of the finger below a reference plane defined by a lower surface of the bond pad by etching the portion of the finger so that the lower surface of the bond pad lies below a surface of a die pad;    mounting a die on the die pad, wherein a lower surface of the die pad is positioned adjacent to the reference plane;    coupling a terminal on the die to the bond pads;    encapsulating the die, the die pad, the bond pads and the portions of the finger with an encapsulating material to form an integrated circuit package; and    removing the encapsulating material adjacent the reference plane to expose the bond pad.    
   
   
       20 . The method of  claim 19 , wherein placing the portion of the finger below a reference plane defined by a lower surface of the bond pad comprises upsetting the bond pad and the die pad relative to the finger and the at least partially surrounding frame.  
   
   
       21 . The method of  claim 19 , wherein mounting the die on the die pad further comprises adhering the die to the die pad with a double backed adhesive tape.  
   
   
       22 . The method of  claim 19 , wherein mounting the die on the die pad further comprises securing the die to the die pad using an adhesive material.  
   
   
       23 . The method of  claim 19 , further comprising bonding a solder ball to a surface of the bond pad.  
   
   
       24 . The method of  claim 23 , further comprising affixing the solder ball to a terminal on a motherboard to couple the die to a system.  
   
   
       25 . The method of  claim 19 , further comprising applying a layer of a metal to the die pad.  
   
   
       26 . A method of providing an electrical contact for a semiconductor package, comprising: 
 including the electrical contact in a leadframe structure;    encapsulating a first portion of the leadframe structure that includes the electrical contact while a second portion of the leadframe structure remains non-encapsulated;    removing the second portion of the leadframe structure from the first portion; and    exposing the electrical contact.    
   
   
       27 . The method of  claim 26 , wherein encapsulating a first portion of the leadframe structure comprises providing an interstitial material to the first portion.  
   
   
       28 . The method of  claim 26 , wherein removing the second portion of the leadframe structure comprises grinding the second portion until the electrical contact is uncovered.  
   
   
       29 . The method of  claim 28 , wherein grinding the second portion comprises grinding a bottom surface of the second portion.  
   
   
       30 . A method of modifying an in-process package that includes a leadframe structure, comprising: 
 encapsulating the in-process package to provide a first portion of the leadframe structure that is coupled to a semiconductor die and a second portion extending away from the semiconductor die;    separating the first portion of the leadframe structure from the second portion of the leadframe structure; and    exposing a region within a perimeter of the interstitial material that includes the interstitial material and the first portion.    
   
   
       31 . The method of  claim 30 , wherein encapsulating the in-process package comprises providing an interstitial material to the in-process package.  
   
   
       32 . The method of  claim 30 , wherein separating the first portion of the leadframe structure from the second portion of the leadframe structure comprises grinding the in-process package to remove the second portion.  
   
   
       33 . The method of  claim 30 , wherein exposing a region comprises revealing an electrical contact that is coupled to the semiconductor die.  
   
   
       34 . A method of modifying an in-process package that includes a leadframe structure, comprising: 
 encapsulating the in-process package to define a first portion of the leadframe structure that is coupled to a semiconductor die and a second portion extending away from the semiconductor die;    removing at least part of the second portion of the leadframe structure; and    exposing at least one electrical contact positioned within the first portion.    
   
   
       35 . The method of  claim 34 , wherein removing at least part of the second portion comprises subjecting the second portion of the in-process package to a material removing operation.  
   
   
       36 . The method of  claim 35 , wherein subjecting the second portion of the in-process package to a material removing operation comprises grinding the second portion of the in-process package.  
   
   
       37 . The method of  claim 34 , wherein encapsulating the in-process package comprises providing an interstitial material to the in-process package.  
   
   
       38 . A package, comprising: 
 an interstitial material encapsulating the package; and    at least a portion of a leadframe structure that is flush with the interstitial material.    
   
   
       39 . The package of  claim 38 , wherein the interstitial material comprises a moldable material.  
   
   
       40 . The package of  claim 39 , wherein the moldable material comprises a thermosetting material.  
   
   
       41 . The package of  claim 38 , wherein the leadframe structure comprises one or more bond pads.  
   
   
       42 . The package of  claim 41 , wherein the leadframe structure comprises a first portion that includes the one or more bond pads, and a second portion extending outwardly from the first portion.  
   
   
       43 . The package of  claim 38 , wherein the interstitial material defines a perimeter of the package, and the leadframe structure extends at least to the perimeter of the package.  
   
   
       44 . The package of  claim 43 , wherein the leadframe structure does not extend beyond the perimeter of the package.  
   
   
       45 . The package of  claim 38 , wherein the package comprises an in-process package.  
   
   
       46 . The package of  claim 38 , wherein the package further comprises a semiconductor die.  
   
   
       47 . The package of  claim 46 , wherein the package comprises a die pad region that retains the semiconductor die.