Cmos and mos device

Abstract

A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first active region and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate; the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.

1 . A complementary metal-oxide-semiconductor (CMOS) device, comprising: 
 a substrate having a first active region and a second active region, wherein the first active region and the second active region are isolated from each other through an isolation structure;    a first type of metal-oxide-semiconductor (MOS) transistor disposed in the first active region of the substrate;    a second type of MOS transistor disposed in the second active region of the substrate;    a etching stop layer covering conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure;    a first stress layer disposed on the etching stop layer in the first active region; and    a second stress layer disposed on the etching stop layer in the second active region.    
   
   
       2 . The CMOS device of  claim 1 , wherein the material constituting the first etching stop layer and the second etching stop layer comprise silicon oxide, silicon oxynitride, silicon carbide, silicon carbonate or silicon-carbon nitride.  
   
   
       3 . The CMOS device of  claim 1 , wherein each of the first etching stop layer and the second etching stop layer has a thickness between 50 Ř200 Å.  
   
   
       4 . The CMOS device of  claim 1 , wherein the material constituting the first stress layer and the second stress layer comprise silicon nitride.  
   
   
       5 . The CMOS device of  claim 1 , wherein the first type of MOS transistor is an N-type MOS (NMOS) transistor and the second type of MOS transistor is a P-type MOS (PMOS) transistor, then the first stress layer is a tensile stress layer and the second stress layer is a compressive stress layer.  
   
   
       6 . The CMOS device of  claim 1 , wherein the first type of MOS transistor is a P-type MOS (PMOS) transistor and the second type of MOS transistor is an N-type MOS (NMOS) transistor, then the first stress layer is a compressive stress layer and the second stress layer is a tensile stress layer.  
   
   
       7 . A metal-oxide-semiconductor (MOS) device, comprising: 
 a substrate;    a conductive type MOS transistor disposed on the substrate;    a etching stop layer covering conformably the conductive type MOS transistor; and    a stress layer disposed on the etching stop layer.    
   
   
       8 . The MOS device of  claim 7 , wherein the material constituting the etching stop layer comprises silicon oxide, silicon oxynitride, silicon carbide, silicon carbonate or silicon-carbon nitride.  
   
   
       9 . The MOS device of  claim 7 , wherein the etching stop layer has a thickness between 50 Ř200 Å.  
   
   
       10 . The MOS device of  claim 7 , wherein the material constituting the stress layer comprises silicon nitride.  
   
   
       11 . The MOS device of  claim 7 , wherein the conductive MOS transistor is an N-type MOS (NMOS) transistor and the stress layer is a tensile stress layer.  
   
   
       12 . The MOS device of  claim 7 , wherein the conductive MOS transistor is a P-type MOS (PMOS) transistor and the stress layer is a compressive stress layer.