US2007123035A1PendingUtilityA1
Method of manufacturing semiconductor device
Est. expiryNov 29, 2025(expired)· nominal 20-yr term from priority
B01D 35/153G01M 3/04H10W 20/085H10W 20/074
47
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Claims
Abstract
A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH 4 gas and CO 2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.
Claims
exact text as granted — not AI-modified1 . A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section, comprising:
forming an interlayer insulation film made of a low dielectric constant material over a wiring layer; forming a silicon oxide film by CVD using SiH 4 gas and CO 2 gas over the interlayer insulation film; forming a chemically amplified resist film to cover the silicon oxide film; and forming a first opening in a position over the chemically amplified resist film where the vertical wiring section is to be formed.
2 . A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section, comprising:
forming an interlayer insulation film made of a low dielectric constant material over a wiring layer; forming a silicon oxide film by CVD using SiH 4 gas and CO 2 gas over the interlayer insulation film; forming a chemically amplified resist film to cover the silicon oxide film; forming a first opening in a position over the chemically amplified resist film where the vertical wiring section is to be formed; forming a second opening by etching the silicon oxide film and the interlayer insulation film while using the chemically amplified resist film as a mask; and forming the vertical wiring section by filling the second opening with a conductive material.
3 . The method of manufacturing a semiconductor device according to claim 1 , wherein a flow rate of the SiH 4 gas: a flow rate of the CO 2 gas in a standard condition is in a range of 1:100-1:400 in forming the silicon oxide film.
4 . The method of manufacturing a semiconductor device according to claim 1 , wherein a heating temperature is in a range of 350° C.-500° C. in forming the silicon oxide film.
5 . The method of manufacturing a semiconductor device according to claim 1 , wherein a pressure is in a range of 400 Pa-666 Pa in forming the silicon oxide film.
6 . The method of manufacturing a semiconductor device according to claim 1 , wherein an input power is in a range of 400 W-600 W in forming the silicon oxide film.
7 . The method of manufacturing a semiconductor device according to claim 1 , further comprising:
forming an antireflection film containing nitrogen by CVD between forming the silicon oxide film and forming the chemically amplified resist film.
8 . The method of manufacturing a semiconductor device according to claim 7 , wherein the antireflection film includes a silicon nitride film.
9 . The method of manufacturing a semiconductor device according to claim 8 , wherein the antireflection film is formed by plasma CVD using SiH 4 gas, NH 3 gas, and N 2 gas in forming the antireflection film.
10 . The method of manufacturing a semiconductor device according to claim 8 , wherein the silicon oxide film and the antireflection film are formed in the same processing chamber.
11 . A method of manufacturing a semiconductor device comprising a wiring structure formed using a dual damascene process, comprising;
sequentially forming a first interlayer insulation film and a second interlayer insulation film, at least one of the first and second interlayer insulation films being made of a low dielectric constant material; forming a silicon oxide film by CVD using SiH 4 gas and CO 2 gas over the second interlayer insulation film; forming a first chemically amplified resist film to cover the silicon oxide film; forming a pattern of an opening over the first chemically amplified resist film; forming a via hole to extend through the silicon oxide film, the first interlayer insulation film, and the second interlayer insulation film, while using the pattern formed over the first chemically amplified resist film as a mask; filling the via hole with a filler; forming a second chemically amplified resist film to cover the second interlayer insulation film and the filler; forming a pattern of a wiring groove in an area of the second chemically amplified resist film including the via hole; forming the wiring groove by etching the second interlayer insulation film while using the second chemically amplified resist film as a mask; and filling the via hole and the wiring groove with a conductive material.
12 . The method of manufacturing a semiconductor device according to claim 11 , further comprising:
forming an antireflection film containing nitrogen by CVD between forming the silicon oxide film and forming the first chemically amplified resist film.
13 . The method of manufacturing a semiconductor device according to claim 1 , wherein the low dielectric constant material is any one of a SiOC film, a SiOF film, a SiO 2 -B 2 O 3 film, a porous silica film, and an organosiloxane film.
14 . The method of manufacturing a semiconductor device according to claim 2 , wherein the low dielectric constant material is any one of a SiOC film, a SiOF film, a SiO 2 -B 2 O 3 film, a porous silica film, and an organosiloxane film.
15 . The method of manufacturing a semiconductor device according to claim 11 , wherein the low dielectric constant material is any one of a SiOC film, a SiOF film, a SiO 2 -B 2 O 3 film, a porous silica film, and an organosiloxane film.Cited by (0)
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