Nonvolatile semiconductor memory device including nand-type flash memory and the like

Abstract

A nonvolatile semiconductor memory device is provided with a memory cell array, a judgment potential correction circuit, and a readout circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix form, and the array includes a first memory cell as a readout object and a second memory cell disposed adjacent to the first memory cell. The judgment potential correction circuit corrects a judgment potential based on a threshold value of the second memory cell. The readout circuit reads the first memory cell as the readout object by use of the corrected judgment potential.

1 . A nonvolatile semiconductor memory device comprising:
 a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell as a readout object and second memory cells disposed adjacent to the first memory cell;   a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the second memory cells; and   a readout circuit which reads the first memory cell as the readout object by use of the judgment potential corrected by the judgment potential correction circuit.   
   
   
       2 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the first memory cell is connected to a word line and a bit line, and the second memory cells disposed adjacent to the first memory cell includes:   a memory cell connected to the word line connected to the first memory cell; and   a memory cell connected to the bit line connected to the first memory cell.   
   
   
       3 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the first memory cell is connected to a word line and a bit line, and the second memory cells disposed adjacent to the first memory cell includes a memory cell connected to the word line connected to the first memory cell.   
   
   
       4 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein the judgment potential correction circuit obtains, from the threshold values of the second memory cells, a threshold value fluctuation of the first memory cell generated by a parasitic capacity between the first memory cell and the second memory cells, and corrects the judgment potential based on the threshold value fluctuation.   
   
   
       5 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein each of the first and second memory cells stores a plurality of multivalued bits, and a threshold value difference between the bits has a threshold value difference capable of being judged irrespective of the threshold value fluctuation due to a parasitic capacity between the first memory cell and the second memory cells.   
   
   
       6 . The nonvolatile semiconductor memory device according to  claim 5 ,
 wherein each of the first and second memory cells stores four values, and data is disposed from a higher threshold value in order of “01”, “00”, “10”, and “11”.   
   
   
       7 . The nonvolatile semiconductor memory device according to  claim 1 ,
 wherein each of the first and second memory cells is a nonvolatile memory cell having a control gate and a floating gate.   
   
   
       8 . A nonvolatile semiconductor memory device comprising:
 a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell and a third memory cell, the first memory cell being connected to a word line, the second memory cell being disposed adjacent to the first memory cell and connected to the word line and a bit line, and the third memory cell being disposed adjacent to the second memory cell and connected to the bit line;   a write circuit which writes data into the second memory cell after writing data into the first memory cell;   a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the third memory cell disposed adjacent to the second memory cell and connected to the bit line; and   a readout circuit which reads the second memory cell by use of the judgment potential corrected by the judgment potential correction circuit.   
   
   
       9 . The nonvolatile semiconductor memory device according to  claim 8 ,
 wherein the judgment potential correction circuit obtains, from the threshold value of the third memory cell, a threshold value fluctuation of the second memory cell generated by a parasitic capacity between the second memory cell and the third memory cell, and corrects the judgment potential based on the threshold value fluctuation.   
   
   
       10 . The nonvolatile semiconductor memory device according to  claim 8 ,
 wherein the first memory cell is connected to even-number bit line, and the second and third memory cells are connected to odd-number bit line.   
   
   
       11 . The nonvolatile semiconductor memory device according to  claim 5 ,
 wherein each of the first, second, and third memory cells stores a plurality of multivalued bits, and a threshold value difference between the bits has a threshold value difference capable of being judged irrespective of the threshold value fluctuation due to a parasitic capacity among the first, second, and third memory cells.   
   
   
       12 . The nonvolatile semiconductor memory device according to  claim 11 ,
 wherein each of the first, second, and third memory cells stores four values, and data is disposed from a higher threshold value in order of “01”, “00”, “10”, and “11”.   
   
   
       13 . The nonvolatile semiconductor memory device according to  claim 8 ,
 wherein each of the first, second, and third memory cells is a nonvolatile memory cell having a control gate and a floating gate.   
   
   
       14 . A nonvolatile semiconductor memory device comprising:
 a memory cell array including a plurality of memory cells arranged in a matrix form, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, the first memory cell being connected to a first word line and a first bit line, the second memory cell being disposed adjacent to the first memory cell and connected to the first word line, a third memory cell being disposed adjacent to the first memory cell and connected to a second word line and the first bit line, and the fourth memory cell being disposed adjacent to the third memory cell and connected to the second word line; and   a write circuit which writes lower bit data into the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell, and upper bit data into the first memory cell and the second memory cell in this order.   
   
   
       15 . The nonvolatile semiconductor memory device according to  claim 14 , further comprising:
 a judgment potential correction circuit which corrects a judgment potential based on threshold values of the second and third memory cells; and   a readout circuit which reads the first memory cell by use of the judgment potential corrected by the judgment potential correction.   
   
   
       16 . The nonvolatile semiconductor memory device according to  claim 15 ,
 wherein the judgment potential correction circuit:   obtains a fluctuation of the threshold value of the first memory cell generated by the parasitic capacities between the first memory cell and the third memory cell and between the first memory cell and the second memory cell from the threshold values of the second and third memory cells, and   corrects the judgment potential based on the fluctuation of the threshold value.   
   
   
       17 . The nonvolatile semiconductor memory device according to  claim 14 , further comprising:
 a judgment potential correction circuit which corrects a judgment potential based on a threshold value of the third memory cell; and   a readout circuit which reads the first memory cell by use of the judgment potential corrected by the judgment potential correction circuit.   
   
   
       18 . The nonvolatile semiconductor memory device according to  claim 17 ,
 wherein the judgment potential correction circuit:   obtains, from the threshold value of the second memory cell, a fluctuation of the threshold value of the first memory cell generated by a parasitic capacity between the first memory cell and the second memory cell, and   corrects the judgment potential based on the fluctuation of the threshold value.   
   
   
       19 . The nonvolatile semiconductor memory device according to  claim 14 ,
 wherein each of the first, second, third, and fourth memory cells stores a plurality of multivalued bits, and a threshold value difference between the bits has a threshold value difference capable of being judged irrespective of the threshold value fluctuation due to a parasitic capacity among the, second, third, and fourth memory cells.   
   
   
       20 . The nonvolatile semiconductor memory device according to  claim 19 ,
 wherein each of the first, second, third, and fourth memory cells stores four values, and data is disposed from a higher threshold value in order of “00”, “01”, “10”, and “11”.   
   
   
       21 . The nonvolatile semiconductor memory device according to  claim 14 ,
 wherein each of the first, second, third, and fourth memory cells is a nonvolatile memory cell having a control gate and a floating gate.