MOS Transistors Including Silicide Layers on Source/Drain Regions

Abstract

A MOS transistor can include a substrate and a field region formed at the semiconductor substrate to define an active region. An I-shaped spacer is on sidewalls of the gate electrode. A lightly doped region and a heavily doped region are on the semiconductor substrate on sides of the gate electrode. A first silicide layer is on a surface of the heavily doped region and a second silicide layer is on the lightly doped region between the I-shaped spacer and the first silicide layer.

1 . A MOS transistor comprising: 
 a substrate;    a field region on the semiconductor substrate to define an active region;    an I-shaped spacer on sidewalls of the gate electrode;    a lightly doped region and a heavily doped region n the semiconductor substrate on sides of the gate electrode;    a first silicide layer on a surface of the heavily doped region; and    a second silicide layer on the lightly doped region between the I-shaped spacer and the first silicide layer.    
   
   
       2 . The MOS transistor as claimed in  claim 1 , wherein the second silicide layer is thinner than the first silicide layer.  
   
   
       3 . The MOS transistor as claimed in  claim 1 , further comprising a gate silicide layer on the gate electrode.  
   
   
       4 . A MOS transistor comprising: 
 a first silicide layer having a first thickness on a source/drain region self-aligned to a sidewall spacer of a gate electrode; and    a second silicide layer having a second thickness, less than the first thickness, on the source/drain region adjacent to the first silicide layer.    
   
   
       5 . The MOS transistor according to  claim 4  further comprising: 
 lightly and heavily doped source/drain regions adjacent to one another in a substrate having the gate electrode with the sidewall spacer thereon;    
   
   
       6 . The MOS transistor according to  claim 4  wherein a surface of the first silicide layer extends beyond an adjacent surface of the second silicide layer.  
   
   
       7 . The MOS transistor according to  claim 4  wherein the first silicide layer extends deeper into the source/drain region that the second silicide layer.  
   
   
       8 . The MOS transistor according to  claim 4  wherein the first silicide layer is elevated farther above the source/drain region that the second silicide layer.