Cmos semiconductor devices having dual work function metal gate stacks

Abstract

CMOS semiconductor devices having dual work function metal gate structures that are formed using fabrication techniques that enable independent work function control for PMOS and NMOS device and which significantly reduce or otherwise eliminate impact on gate dielectric reliability.

1 . A semiconductor device, comprising:
 a semiconductor substrate having a dual-gate CMOS device formed on the semiconductor substrate, the dual-gate CMOS device comprising a PMOS device and an NMOS device,   wherein the PMOS device has a first gate stack comprising:
 a gate insulating layer formed on the semiconductor substrate; 
 a first conductive layer formed on the gate insulating layer; 
 a second conductive layer formed on the first conductive layer; and 
 a third conductive layer formed on the second conductive layer, 
   wherein the NMOS device has a second gate stack comprising:
 a gate insulating layer formed on the semiconductor substrate; 
 a first conductive layer formed on the gate insulating layer; and 
 a second conductive layer formed on the first conductive layer, and 
   wherein the second conductive layers of the first and second gate stacks are formed from different conductive materials.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the first conductive layers of the first and second gate stacks are formed of a same conductive material and have a substantially same thickness. 
   
   
       3 . The semiconductor device of  claim 2 , wherein the first conductive layers of the first and second gate stacks are formed of a metallic nitride. 
   
   
       4 . The semiconductor device of  claim 3 , wherein the first conductive layers of the first and second gate stack are formed of TaN or TiN. 
   
   
       5 . The semiconductor device of  claim 2 , wherein the thickness and the conductive material of the first conductive layers of the first and second gate stacks is selected to modulate a work function of the NMOS device. 
   
   
       6 . The semiconductor device of  claim 2 , wherein a thickness and a conductive material of the second conductive layer of the first gate stack is selected to modulate a function of the PMOS device. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the first and second conductive layers of the first gate stack are formed of different metallic nitride materials. 
   
   
       8 . The semiconductor device of  claim 7 , wherein the metallic nitride materials include TiN, TaN, or AlN. 
   
   
       9 . The semiconductor device of  claim 1 , wherein the first, second and third conductive layers of the first gate stack are formed of different conductive materials. 
   
   
       10 . The semiconductor device of  claim 9 , wherein the first conductive layer is formed of a material that has an etch selectivity that is larger than an etch selectivity of the different materials that form the second and third conductive layers of the first gate stack with regard to an HF etching solution. 
   
   
       11 . The semiconductor device of  claim 10 , wherein the first, second and third conductive layers of the first gate stack of the PMOS device are formed of TaN, AlN and HfN, respectively. 
   
   
       12 . The semiconductor device of  claim 10 , wherein the first, second and third conductive layers of the first gate stack of the PMOS device are formed of HfN, AlN and TaN, respectively. 
   
   
       13 . The semiconductor device of  claim 1 , wherein the gate insulating layers of the first and second gate stacks is formed of a dielectric material having a dielectric constant in a range of about 8 and greater. 
   
   
       14 . The semiconductor of  claim 13 , further comprising an interfacial layer interposed between the gate insulating layers and the semiconductor substrate. 
   
   
       15 . The semiconductor device of  claim 13 , wherein the gate insulating layers of the first and second gate stacks are formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, yttrium oxide, or aluminum oxide. 
   
   
       16 . The semiconductor device of  claim 1 , wherein the first gate stack of the PMOS device further comprises a fourth conductive layer formed on the third conductive layer. 
   
   
       17 . The semiconductor device of  claim 16 , wherein the second conductive layer of the second gate stack and the fourth conductive layer of the first gate stack are formed of a same conductive material. 
   
   
       18 . The semiconductor device of  claim 16 , wherein the second conductive layer of the second gate stack and the fourth conductive layer of the first gate stack are formed of a polysilicon material. 
   
   
       19 . The semiconductor device of  claim 1 , wherein the thickness of first conductive layers of the first and second gate stacks is in a range of about 5 angstroms to about 60 angstroms. 
   
   
       20 . A semiconductor device, comprising:
 a semiconductor substrate having a dual-gate CMOS device formed on a front-side of the semiconductor substrate, the dual-gate CMOS device comprising a PMOS device having a first MIPS gate stack, and an NMOS device having a second MIPS gate stack,   wherein the first and second MIPS gate stacks each comprise:
 a gate insulating layer formed on the semiconductor substrate; 
 a polysilicon electrode; and 
 a metal inserted layer interposed between the gate insulating layer and the polysilicon electrode, 
   wherein the metal inserted layer of the first MIPS gate stack comprises a stack of at least first, second and third metallic layers; and   wherein the metal inserted layer of the second MIPS gate stack comprises at least a first metallic layer.   
   
   
       21 . The semiconductor device of  claim 20 , wherein the first metallic layers of the first and second MIPS gate stacks are formed of a same metallic material and have a same thickness in a range of about 5 angstroms to about 60 angstroms. 
   
   
       22 . The semiconductor device of  claim 21 , wherein the first metallic layers of the first and second MIPS gate stacks are formed of a metallic nitride 
   
   
       23 . The semiconductor device of  claim 22 , wherein the thickness and the metallic nitride material of the first conductive layers of the first and second MIPS gate stacks is selected to modulate a work function of the NMOS device. 
   
   
       24 . The semiconductor device of  claim 21 , wherein a thickness and a conductive material of the second metallic layer of the first MIPS gate stack is selected to modulate a work function of the PMOS device. 
   
   
       25 . The semiconductor device of  claim 20 , wherein the first, second and third metallic layers of the first MIPS gate stack are formed of different conductive materials. 
   
   
       26 . The semiconductor device of  claim 25 , wherein the first, second and third metallic layers of the first MIPS gate stack are formed of TaN, AlN and HfN, respectively. 
   
   
       27 . The semiconductor device of  claim 25 , wherein the first, second and third metallic layers of the first MIPS gate stack are formed of HfN, AlN and TaN, respectively. 
   
   
       28 . The semiconductor device of  claim 20 , wherein the gate ins insulating layers of the first and second MIPS stacks are formed of a dielectric material having a dielectric constant in a range of about 8 and greater. 
   
   
       29 . The semiconductor of  claim 20 , further comprising an interfacial layer interposed between the gate insulating layers and the semiconductor substrate. 
   
   
       30 . A method for fabricating a semiconductor device having a dual-gate CMOS device, the method comprising:
 defining an active region of a CMOS device on a semiconductor substrate, the active region comprising an NMOS device region and a PMOS device region;   forming a gate insulating layer on the semiconductor substrate;   forming a first conductive layer on the gate insulating layer;   forming a second conductive layer on the first conductive layer;   forming third conductive layer on the second conductive layer;   performing an etch process to etch the third and second conductive layers down to the first conductive layer in the NMOS device region; and   forming a first gate structure in the PMOS region and second gate structure in the NMOS region, wherein the first gate structure is stacked structure formed from the gate insulating layer and first and second conductive layers, and wherein the second gate structure is a stacked structure formed from the gate insulating layer and the first conductive layer.   
   
   
       31 . The method of  claim 30 , wherein the third and second conductive layers are etched using an etch process wherein an etch selectivity of the first conductive layer is larger than an etch selectivity of the second and third conductive layers such that the first conductive layer serves as an etch stop. 
   
   
       32 . The method of  claim 31 , wherein the etch process is a wet etch process using an HF solution. 
   
   
       33 . The method of  claim 32 , wherein the first conductive layer is formed of TaN, wherein the second conductive layer is formed of AlN and wherein the third conductive layer is formed of HfN. 
   
   
       34 . The method of  claim 30 , wherein forming the first and second gate structures comprises:
 forming a fourth conductive layer over the NMOS and PMOS regions;   forming an etch mask on the fourth conductive layer, wherein the etch mask defines a gate pattern for the first and second gate structures;   etching the fourth conductive layer downs to the substrate to form the first and second gate structures.   
   
   
       35 . The method of  claim 34 , wherein the fourth conductive layer comprises polysilicon. 
   
   
       36 . The method of  claim 34 , wherein the fourth conductive layer comprises a metallic material. 
   
   
       37 . The method of  claim 36 , wherein the fourth conductive layer comprises a metal silicide or nitride material. 
   
   
       38 . The method of  claim 30 , wherein forming the gate insulating layer comprises:
 forming an interfacial layer on the semiconductor substrate; and   forming a layer of gate dielectric material over the interfacial layer.   
   
   
       39 . The method of  claim 38 , wherein the gate dielectric material has a dielectric constant in a range of about 8 and greater. 
   
   
       40 . The method of  claim 39 , wherein the gate dielectric material gate insulating layers of the first and second gate stacks are formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, yttrium oxide, or aluminum oxide.