Mosfet wth high angle sidewall gate and contacts for reduced miller capacitance

Abstract

The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

1 . A method for fabricating an FET device, comprising: 
 forming a gate dielectric layer over a semiconductor substrate;    forming a gate conductor layer over the gate dielectric layer;    selectively patterning the gate conductor layer to form a conductive gate electrode that has a top, a base, and sidewalls, wherein the sidewalls of said conductive gate electrode are offset from a vertical direction by an offset angle that is greater than about 0° and not more than about 45°, so that the top of said conductive gate electrode has a surface area smaller than that of the base; and    forming source and drain regions in the semiconductor substrate.    
   
   
       2 . The method of  claim 1 , wherein the offset angle ranges from about 10° to about 20°.  
   
   
       3 . The method of  claim 1 , wherein the conductive gate electrode is formed by a reactive ion etching (RIE) process.  
   
   
       4 . The method of  claim 1 , further comprising forming a source extension region and a drain extension region in the semiconductor substrate before formation of the source and drain regions.  
   
   
       5 . The method of  claim 1 , further comprising forming a source/drain spacer along each of the sidewalls of the conductive gate electrode before formation of the source and drain regions.  
   
   
       6 . The method of  claim 1 , further comprising forming metal silicide conductors for the gate electrode, the source region, and the drain region.  
   
   
       7 . The method of  claim 1 , further comprising forming a capping layer over the conductive gate electrode, the source region, and the drain region.  
   
   
       8 . The method of  claim 1 , further comprising forming metal contacts for the source and drain regions, wherein each of said metal contacts has a top, a base, and sidewalls, wherein the sidewalls of each metal contact are offset from a vertical direction by an offset angle that is greater than about 0° and not more than about 45°, so that the top of said metal contact has a surface area larger than that of the base.